Philips Semiconductors
Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
Pin description for SQFP208
SYMBOL
VSSD0
PIN
STATUS
DESCRIPTION
1
P
I/O
I/O
I/O
I/O
P
digital ground 0
D1_A0
D1_A1
D1_A2
D1_A3
VDDD1
n.c.
2
bidirectional digital CCIR 656 D1 port A bit 0
bidirectional digital CCIR 656 D1 port A bit 1
bidirectional digital CCIR 656 D1 port A bit 2
bidirectional digital CCIR 656 D1 port A bit 3
digital supply voltage 1 (3.3 V)
3
4
5
6
7
−
reserved pin; not connected internally
digital ground 1
VSSD1
D1_A4
D1_A5
D1_A6
D1_A7
VDDD2
n.c.
8
P
9
I/O
I/O
I/O
I/O
P
bidirectional digital CCIR 656 D1 port A bit 4
bidirectional digital CCIR 656 D1 port A bit 5
bidirectional digital CCIR 656 D1 port A bit 6
bidirectional digital CCIR 656 D1 port A bit 7
digital supply voltage 2 (3.3 V)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
−
reserved pin; not connected internally
digital ground 2
VSSD2
VS_A
HS_A
LLC_A
PXQ_A
n.c.
P
I/O
I/O
I/O
I/O
−
bidirectional vertical sync signal port A
bidirectional horizontal sync signal port A
bidirectional line-locked system clock port A
bidirectional pixel qualifier signal to mark valid pixels port A; note 1
reserved pin; do not connect
VDDD3
n.c.
P
digital supply voltage 3 (3.3 V)
−
reserved pin; not connected internally
digital ground 3
VSSD3
TRST
TMS
P
I
test reset input (JTAG pin must be set LOW for normal operation)
I
test mode select input (JTAG pin must be floating or set to HIGH during normal
operation)
TCLK
TDO
26
27
28
29
30
31
32
33
34
35
36
37
38
I
O
I
test clock input (JTAG pin should be set LOW during normal operation)
test data output (JTAG pin not active during normal operation)
test data input (JTAG pin must be floating or set to HIGH during normal operation)
digital supply voltage 4 (3.3 V)
TDI
VDDD4
n.c.
P
−
P
O
I
reserved pin; not connected internally
VSSD4
INTA#
RST#
CLK
digital ground 4
PCI interrupt line output (active LOW)
PCI global reset input (active LOW)
I
PCI clock input
GNT#
REQ#
VDDD5
n.c.
I
bus grant input signal input, PCI arbitration signal (active LOW)
bus request output signal output, PCI arbitration signal (active LOW)
digital supply voltage 5 (3.3 V)
O
P
−
reserved pin; not connected internally
1998 Apr 09
11
NXP [ NXP ]
