Philips Semiconductors
Preliminary specification
PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler
SAA7114H
SYMBOL
RTCO
PIN
TYPE
DESCRIPTION
36
(I/)O real-time control output; contains information about actual system clock
frequency, field rate, odd/even sequence, decoder status, subcarrier frequency
and phase and PAL sequence (see external document “RTC Functional
Description”, available on request); the RTCO pin is enabled via I2C-bus
bit RTCE; see notes 2, 3 and Table 34
AMCLK
VSSD(ICO1)
ASCLK
37
38
39
40
O
P
audio master clock output, up to 50% of crystal clock
internal digital core supply ground 1
audio serial clock output
O
ALRCLK
(I/)O audio left/right clock output; can be strapped to supply via a 3.3 kΩ resistor to
indicate that the default 24.576 MHz crystal (ALRCLK = 0; internal pull-down)
has been replaced by a 32.110 MHz crystal (ALRCLK = 1); see notes 2 and 4
AMXCLK
ITRDY
41
42
43
44
45
I
I
audio master external clock input
target ready input, image port (with internal pull-up)
internal digital core supply voltage 2 (+3.3 V)
VDDD(ICO2)
TEST0
ICLK
P
O
I/O
do not connect; reserved for future extensions and for testing: scan output
clock output signal for image port, or optional asynchronous back-end clock
input
IDQ
ITRI
46
47
O
output data qualifier for image port (optional: gated clock output)
I(/O) image port output control signal, effects all input port pins inclusive ICLK, enable
and active polarity is under software control (bits IPE in subaddress 87H); output
path used for testing: scan output
IGP0
IGP1
48
49
O
general purpose output signal 0; image port (controlled by subaddresses
84H and 85H)
O
general purpose output signal 1; image port (controlled by subaddresses
84H and 85H)
VSSD(EP2)
VDDD(EP3)
IGPV
50
51
52
P
P
O
external digital pad supply ground 2
external digital pad supply voltage 3 (+3.3 V)
multi purpose vertical reference output signal; image port (controlled by
subaddresses 84H and 85H)
IGPH
53
O
multi purpose horizontal reference output signal; image port (controlled by
subaddresses 84H and 85H)
IPD7 to IPD4
VDDD(ICO3)
54 to 57
58
O
P
O
P
I/O
P
I/O
I
image port data outputs
internal digital core supply voltage 3 (+3.3 V)
IPD3 to IPD0
VSSD(ICO2)
59 to 62
63
image port data output
internal digital core supply ground 2
HPD7 to HPD4 64 to 67
VDDD(ICO4) 68
HPD3 to HPD0 69 to 72
host port data I/O, carries UV chrominance information in 16-bit video I/O modes
internal digital core supply voltage 4 (+3.3 V)
host port data I/O, carries UV chrominance information in 16-bit video I/O modes
do not connect; reserved for future extensions and for testing: scan input
do not connect; reserved for future extensions and for testing: scan input
external digital pad supply voltage 4 (+3.3 V)
TEST1
73
74
75
76
77
TEST2
I
VDDD(EP4)
VSSD(EP3)
TEST3
P
P
I
external digital pad supply ground 3
do not connect; reserved for future extensions and for testing: scan input
2000 Mar 15
8
NXP [ NXP ]
