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i
[
]
LLC2
RTS0
XCLK XPD 7:0
XRV
XTRI
TEST5
TEST3
TEST1
TEST0
[
]
LLC
RTCO
(1)
RTS1 XDQ
XRH
XRDY
HPD 7:0
SDA SCL
TEST4
TEST2
28 29 36 34 35 94 95
81, 82,
84 to 87
89, 90
92 91 96 80
64 to 67,
69 to 72
32
31
79 78 77 74 73 44
2
REAL-TIME OUTPUT
EXPANSION PORT PIN MAPPING
I/O CONTROL
I C-BUS
30
27
4
RES
CE
chrominance of 16-bit input
X PORT I/O FORMATTING
CLOCK GENERATION
AND
POWER-ON CONTROL
54 to 57,
59 to 62
XTOUT
XTALI
XTALO
SAA7114H
7
PROGRAMMING
REGISTER
ARRAY
A/B
REGISTER
MUX
[
]
IPD 7:0
6
46
53
52
48
49
IDQ
20
18
16
14
12
10
22
AI11
AI12
IGPH
IGPV
IGP0
IGP1
EVENT CONTROLLER
DIGITAL
AI21
DECODER
ANALOG
WITH
AI22
DUAL
ADC
FIR-PREFILTER
PRESCALER
AND
HORIZONTAL
ADAPTIVE
COMB
LINE
VERTICAL
FIFO
FINE
(PHASE)
SCALING
AI23
VIDEO
FIFO
SCALING
BUFFER
FILTER
AI24
SCALER BCS
32
to
8(16)
MUX
AOUT
45
19
13
ICLK
AI1D
AI2D
BOUNDARY
SCAN
AUDIO
CLOCK
GENERATION
GENERAL PURPOSE
VBI-DATA SLICER
TEXT
FIFO
TEST
42
47
21
AGND
ITRDY
ITRI
VIDEO/TEXT
ARBITER
33, 43,
1, 25,
23, 17, 38, 63,
26, 50, 24,
58, 68,
83, 93
97 98 99
3
2
37 40 39 41
8
5
51, 75
11
88
76, 100 15, 9
MHB528
V
AMCLK ASCLK
TCK
TDI
V
V
V
V
DD(XTAL)
DDD(ICO1)
DDA0
to
DDA2
SSD(EP1)
to
to
TMS TDO
ALRCLK AMXCLK
(1)
V
V
TRST
DDD(ICO6)
SSD(EP4)
V
V
V
V
V
V
SS(XTAL)
DDD(EP1)
to
DDD(EP4)
SSD(ICO1)
to
SSD(ICO3)
SSA0
to
SSA2
V
(1) The pins RTCO and ALRCLK are used for configuration of the I2C-bus interface
and the definition of the crystal oscillator frequency at RESET (pin strapping).
Fig.1 Block diagram.
NXP [ NXP ]
