Philips Semiconductors
Preliminary specification
PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler
SAA7114H
7
PINNING
SYMBOL
PIN
TYPE
DESCRIPTION
VDDD(EP1)
1
2
3
4
5
6
P
O
I
external digital pad supply voltage 1 (+3.3 V)
test data output for boundary scan test; note 1
test data input for boundary scan test; note 1
crystal oscillator output signal; auxiliary signal
ground for crystal oscillator
TDO
TDI
XTOUT
VSS(XTAL)
XTALO
O
P
O
24.576 MHz (32.11 MHz) crystal oscillator output; not connected if TTL clock
input of XTALI is used
XTALI
7
I
input terminal for 24.576 MHz (32.11 MHz) crystal oscillator or connection of
external oscillator with TTL compatible square wave clock signal
VDD(XTAL)
VSSA2
AI24
8
P
P
I
supply voltage for crystal oscillator
ground for analog inputs AI2n
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
analog input 24
VDDA2
AI23
P
I
analog supply voltage for analog inputs AI2n (+3.3 V)
analog input 23
AI2D
I
differential input for ADC channel 2 (pins AI24, AI23, AI22 and AI21)
analog input 22
AI22
I
VSSA1
AI21
P
I
ground for analog inputs AI1n
analog input 21
VDDA1
AI12
P
I
analog supply voltage for analog inputs AI1n (+3.3 V)
analog input 12
AI1D
I
differential input for ADC channel 1 (pins AI12 and AI11)
analog input 11
AI11
I
AGND
AOUT
VDDA0
VSSA0
VDDD(EP2)
VSSD(EP1)
CE
P
O
P
P
P
P
I
analog ground connection
do not connect; analog test output
analog supply voltage (+3.3 V) for internal Clock Generation Circuit (CGC)
ground for internal clock generation circuit
external digital pad supply voltage 2 (+3.3 V)
external digital pad supply ground 1
chip enable or reset input (with internal pull-up)
line-locked system clock output (27 MHz nominal)
line-locked 1⁄2 clock output (13.5 MHz nominal)
reset output (active LOW)
LLC
O
O
O
LLC2
RES
SCL
I(/O) serial clock input (I2C-bus) with inactive output path
SDA
I/O
P
serial data input/output (I2C-bus)
VDDD(ICO1)
RTS0
RTS1
internal digital core supply voltage 1 (+3.3 V)
O
real-time status or sync information, controlled by subaddresses 11H and 12H;
see Section 15.2.18, 15.2.19 and 15.2.20
O
2000 Mar 15
7
NXP [ NXP ]
