Philips Semiconductors
Preliminary specification
PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler
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PINNING
SYMBOL
V
DDD(EP1)
TDO
TDI
XTOUT
V
SS(XTAL)
XTALO
XTALI
V
DD(XTAL)
V
SSA2
AI24
V
DDA2
AI23
AI2D
AI22
V
SSA1
AI21
V
DDA1
AI12
AI1D
AI11
AGND
AOUT
V
DDA0
V
SSA0
V
DDD(EP2)
V
SSD(EP1)
CE
LLC
LLC2
RES
SCL
SDA
V
DDD(ICO1)
RTS0
RTS1
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
TYPE
P
O
I
O
P
O
I
P
P
I
P
I
I
I
P
I
P
I
I
I
P
O
P
P
P
P
I
O
O
O
I(/O)
I/O
P
O
O
DESCRIPTION
external digital pad supply voltage 1 (+3.3 V)
test data output for boundary scan test; note 1
test data input for boundary scan test; note 1
crystal oscillator output signal; auxiliary signal
ground for crystal oscillator
SAA7114H
24.576 MHz (32.11 MHz) crystal oscillator output; not connected if TTL clock
input of XTALI is used
input terminal for 24.576 MHz (32.11 MHz) crystal oscillator or connection of
external oscillator with TTL compatible square wave clock signal
supply voltage for crystal oscillator
ground for analog inputs AI2n
analog input 24
analog supply voltage for analog inputs AI2n (+3.3 V)
analog input 23
differential input for ADC channel 2 (pins AI24, AI23, AI22 and AI21)
analog input 22
ground for analog inputs AI1n
analog input 21
analog supply voltage for analog inputs AI1n (+3.3 V)
analog input 12
differential input for ADC channel 1 (pins AI12 and AI11)
analog input 11
analog ground connection
do not connect; analog test output
analog supply voltage (+3.3 V) for internal Clock Generation Circuit (CGC)
ground for internal clock generation circuit
external digital pad supply voltage 2 (+3.3 V)
external digital pad supply ground 1
chip enable or reset input (with internal pull-up)
line-locked system clock output (27 MHz nominal)
line-locked
1
⁄
2
clock output (13.5 MHz nominal)
reset output (active LOW)
serial clock input (I
2
C-bus) with inactive output path
serial data input/output (I
2
C-bus)
internal digital core supply voltage 1 (+3.3 V)
real-time status or sync information, controlled by subaddresses 11H and 12H;
see Section 15.2.18, 15.2.19 and 15.2.20
2000 Mar 15
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