Philips Semiconductors
Preliminary specification
PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler
SAA7114H
Table 91 I-port I/O enable, output clock and gated clock phase control; global set 87H[7:4]
CONTROL BITS D7 TO D4(1)
OUTPUT CLOCK AND GATED CLOCK PHASE CONTROL
ICLK default output phase
IPCK3(2) IPCK2(2) IPCK1 IPCK0
X
X
X
X
0
0
0
1
ICLK phase shifted by 1⁄2 clock cycle
recommended for ICKS1 = 1 and
ICKS0 = 0 (subaddress 80H)
ICLK phase shifted by about 3 ns
ICLK phase shifted by 1⁄2 clock cycle + about 3 ns
X
X
0
0
X
X
0
1
1
1
0
1
alternatively to setting ‘01’
recommended for gated
IDQ = gated clock default output phase
IDQ = gated clock phase shifted by 1⁄2 clock cycle
X
X
X
X
clock output
IDQ = gated clock phase shifted by about 3 ns
IDQ = gated clock phase shifted by 1⁄2 clock cycle + about 3 ns
1
1
0
1
X
X
X
X
alternatively
to setting ‘01’
Notes
1. X = don’t care.
2. IPCK3 and IPCK2 only affects the gated clock (subaddress 80H, bit ICKS2 = 1).
Table 92 I-port I/O enable, output clock and gated clock phase control; global set 87H[1:0]
CONTROL BITS D1 AND D0
I-PORT I/O ENABLE
IPE1
IPE0
I-port output is disabled by software
0
0
1
1
0
1
0
1
I-port output is enabled by software
I-port output is enabled by pin ITRI at logic 0
I-port output is enabled by pin ITRI at logic 1
15.5.3 SUBADDRESS 88H
Table 93 Power save control; global set 88H[3] and 88H[1:0]
X = don’t care.
CONTROL BITS
88H[3] 88H[1:0]
POWER SAVE CONTROL
SLM3
SLM1
SLM0
Decoder and VBI slicer are in operational mode
X
X
X
X
0
1
Decoder and VBI slicer are in power-down mode; scaler only operates, if scaler
input and ICLK source is the X-port (refer to subaddresses 80H and 91H/C1H)
Scaler is in operational mode
X
X
0
1
0
1
X
X
X
X
Scaler is in power-down mode; scaler in power-down stops I-port output
Audio clock generation active
X
X
Audio clock generation in power-down and output disabled
2000 Mar 15
115
NXP [ NXP ]
