Philips Semiconductors
Preliminary specification
PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler
SAA7114H
Table 81 Global control 1; global set 80H[6:4]
SWRST moved to subaddress 88H[5]; X = don’t care.
CONTROL BITS D6 TO D4
TASK ENABLE CONTROL
Task of register set A is disabled
SMOD
TEB
TEA
X
X
X
X
0
X
X
0
0
1
Task of register set A is enabled
Task of register set B is disabled
X
X
X
X
Task of register set B is enabled
1
The scaler window defines the F and V timing of the scaler output
VBI-data slicer defines the F and V timing of the scaler output
X
X
1
15.5.2 SUBADDRESSES 83H TO 87H
Table 82 X-port I/O enable and output clock phase control; global set 83H[5:4]
CONTROL BITS D5 AND D4
OUTPUT CLOCK PHASE CONTROL
XPCK1
XPCK0
XCLK default output phase, recommended value
XCLK output inverted
0
0
1
1
0
1
0
1
XCLK phase shifted by about 3 ns
XCLK output inverted and shifted by about 3 ns
Table 83 X-port I/O enable and output clock phase control; global set 83H[2:0]
X = don’t care.
CONTROL BITS D2 TO D0
X-PORT I/O ENABLE
XRQT
XPE1
XPE0
X-port output is disabled by software
X
X
X
X
0
0
0
1
1
X
X
0
1
0
1
X
X
X-port output is enabled by software
X-port output is enabled by pin XTRI at logic 0
X-port output is enabled by pin XTRI at logic 1
XRDY output signal is A/B task flag from event handler (A = 1)
XRDY output signal is ready signal from scaler path (XRDY = 1 means SAA7114H is
ready to receive data)
1
2000 Mar 15
111
NXP [ NXP ]
