Philips Semiconductors
Preliminary specification
PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler
SAA7114H
Table 94 Power save control; global set 88H[7:4]
CONTROL BITS D7 TO D4(1)
POWER SAVE CONTROL
DPROG = 0 after reset
CH4EN
CH2EN SWRST(2) DPROG
X
X
X
X
X
X
0
1
DPROG = 1 can be used to assign that the device has been
programmed; this bit can be monitored in the scalers status byte,
bit PRDON; if DPROG was set to logic 1 and PRDON status bit
shows a logic 0 a power- or start-up fail has occurred
Scaler path is reset to it’s idle state, software reset
Scaler is switched back to operation
X
X
X
X
0
X
X
0
0
1
X
X
X
X
X
X
AD1x analog channel is in power-down mode
AD1x analog channel is active
X
X
X
X
1
AD2x analog channel is in power-down mode
AD2x analog channel is active
X
X
1
Notes
1. X = don’t care.
2. Bit SWRST is now located here.
15.5.4 SUBADDRESS 8FH (READ-ONLY REGISTER)
Table 95 Status information scaler part; 8FH[7:0]
I2C-BUS
BIT
FUNCTION(1)
STATUS BIT
D7
D6
D5
D4
D3
D2
XTRI
ITRI
status on input pin XTRI, if not used for 3-state control, usable as hardware flag for software use
status on input pin ITRI, if not used for 3-state control, usable as hardware flag for software use
status of the internal ‘FIFO almost filled’ flag
FFIL
FFOV
status of the internal ‘FIFO overflow’ flag
PRDON
ERR_OF
copy of bit DPROG, can be used to detect power-up and start-up fails
error flag of scalers output formatter, normally set, if the output processing needs to be
interrupted, due to input/output data rate conflicts, e.g. if output data rate is much too low and all
internal FIFO capacity used
D1
D0
FIDSCI
status of the field sequence ID at the scalers input
FIDSCO
status of the field sequence ID at the scalers output, scaler processing dependent
Note
1. Status information is unsynchronized and shows the actual status at the time of I2C-bus read.
2000 Mar 15
116