欢迎访问ic37.com |
会员登录 免费注册
发布采购

SAA7114H 参数 Datasheet PDF下载

SAA7114H图片预览
型号: SAA7114H
PDF下载: 下载PDF文件 查看货源
内容描述: PAL / NTSC / SECAM视频解码器具有自适应PAL / NTSC梳状滤波器, VBI数据限幅器和高性能的定标器 [PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC combfilter, VBI-data slicer and high performance scaler]
分类和应用: 解码器转换器色度信号转换器消费电路商用集成电路
文件页数/大小: 140 页 / 549 K
品牌: NXP [ NXP ]
 浏览型号SAA7114H的Datasheet PDF文件第103页浏览型号SAA7114H的Datasheet PDF文件第104页浏览型号SAA7114H的Datasheet PDF文件第105页浏览型号SAA7114H的Datasheet PDF文件第106页浏览型号SAA7114H的Datasheet PDF文件第108页浏览型号SAA7114H的Datasheet PDF文件第109页浏览型号SAA7114H的Datasheet PDF文件第110页浏览型号SAA7114H的Datasheet PDF文件第111页  
Philips Semiconductors  
Preliminary specification  
PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC  
comb filter, VBI-data slicer and high performance scaler  
SAA7114H  
15.3.2 SUBADDRESSES 34H TO 36H  
Table 66 Audio master clock (AMCLK) nominal increment  
SUBADDRESS  
CONTROL BITS D7 TO D0  
34H  
35H  
36H  
ACNI7  
ACNI15  
ACNI6  
ACNI14  
ACNI5  
ACNI13  
ACNI21  
ACNI4  
ACNI12  
ACNI20  
ACNI3  
ACNI11  
ACNI19  
ACNI2  
ACNI10  
ACNI18  
ACNI1  
ACNI9  
ACNI17  
ACNI0  
ACNI8  
ACNI16  
15.3.3 SUBADDRESS 38H  
Table 67 Clock ratio AMCLK (audio master clock) to ASCLK (serial bit clock)  
SUBADDRESS  
CONTROL BITS D7 TO D0  
SDIV4 SDIV3  
38H  
SDIV5  
SDIV2  
SDIV1  
SDIV0  
15.3.4 SUBADDRESS 39H  
Table 68 Clock ratio ASCLK (serial bit clock) to ALRCLK (channel select clock)  
SUBADDRESS  
CONTROL BITS D7 TO D0  
LRDIV4 LRDIV3  
39H  
LRDIV5  
LRDIV2  
LRDIV1  
LRDIV0  
15.3.5 SUBADDRESS 3AH  
Table 69 Audio clock control; 3AH[3:0]  
BIT DESCRIPTION SYMBOL VALUE  
FUNCTION  
D3 audio PLL modes  
APLL  
AMVR  
LRPH  
SCPH  
0
1
0
1
0
1
0
1
PLL active, AMCLK is field-locked  
PLL open, AMCLK is free-running  
D2 audio master clock  
vertical reference  
vertical reference pulse is taken from internal decoder  
vertical reference is taken from XRV input (expansion port)  
ALRCLK edges triggered by falling edges of ASCLK  
ALRCLK edges triggered by rising edges of ASCLK  
ASCLK edges triggered by falling edges of AMCLK  
ASCLK edges triggered by rising edges of AMCLK  
D1  
ALRCLK phase  
D0 ASCLK phase  
15.4 Programming register VBI-data slicer  
15.4.1 SUBADDRESS 40H  
Table 70 Slicer control 1; 40H[6:4]  
BIT  
DESCRIPTION  
SYMBOL VALUE  
FUNCTION  
D6 Hamming check  
HAM_N  
0
Hamming check for 2 bytes after framing code,  
dependent on data type (default)  
1
0
1
0
1
no Hamming check  
D5 framing code error  
D4 amplitude searching  
FCE  
one framing code error allowed  
no framing code errors allowed  
amplitude searching active (default)  
amplitude searching stopped  
HUNT_N  
2000 Mar 15  
107  
 复制成功!