Philips Semiconductors
Preliminary specification
PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler
SAA7114H
15.2.27 SUBADDRESS 1FH (READ ONLY REGISTER)
Table 64 Status byte video decoder; 1FH[7:0]
I2C-BUS
OLDSB
BIT
DESCRIPTION
status bit for interlace detection
CONTROL
BIT
VALUE
FUNCTION
14H[2]
D7
INTL
HLVLN
HLCK
−
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
non-interlaced
interlaced
both loops locked
unlocked
locked
D6
status bit for horizontal and vertical loop
status bit for locked horizontal frequency
identification bit for detected field frequency
0
1
−
−
−
−
0
1
0
1
unlocked
50 Hz
D5
D4
D3
D2
D1
FIDT
60 Hz
gain value for active luminance channel is limited;
maximum (top)
GLIMT
GLIMB
WIPA
not active
active
gain value for active luminance channel is limited;
minimum (bottom)
not active
active
white peak loop is activated
not active
active
copy protected source detected according to
macrovision version up to 7.01
COPRO
SLTCA
RDCAP
CODE
not active
active
slow time constant active in WIPA mode
not active
active
D0
ready for capture (all internal loops locked)
not active
active
colour signal in accordance with selected standard has
been detected
not active
active
15.3 Programming register audio clock generation
See equations in Section 8.6 and examples in Tables 21 and 22.
15.3.1 SUBADDRESSES 30H TO 32H
Table 65 Audio master clock (AMCLK) cycles per field
SUBADDRESS
CONTROL BITS D7 TO D0
30H
31H
32H
ACPF7
ACPF15
−
ACPF6
ACPF14
−
ACPF5
ACPF13
−
ACPF4
ACPF12
−
ACPF3
ACPF11
−
ACPF2
ACPF10
−
ACPF1
ACPF9
ACPF17
ACPF0
ACPF8
ACPF16
2000 Mar 15
106
NXP [ NXP ]
