SAA7113H
Philips Semiconductors
9-bit video input processor
8.7 Power-on reset and CE input
A missing clock, insufficient digital or analog VDDA0 supply voltages (below 2.8 V) will
initiate the reset sequence; all outputs are forced to 3-state (see Figure 21).
It is possible to force a reset by pulling the Chip Enable (CE) input to ground. After the
rising edge of CE and sufficient power supply voltage, the outputs LLC and SDA return
from 3-state to active, while RTS0, RTS1 and RTCO remain in 3-state and have to be
activated via I2C-bus programming (see Table 5).
POC V
POC V
DDD
DDA
ANALOG
DIGITAL
CLOCK
PLL
LLC
POC
LOGIC
POC
DELAY
RES
CE
RESINT
CLK0
CE
XTAL
LLCINT
RESINT
LLC
RES
(internal
reset)
20 µs to 200 µs
PLL delay
896 LLC
digital delay
some ms
128 LLC
<
1 ms
mhb331
CE = chip enable input;
XTAL = crystal oscillator output;
LLCINT = internal system clock;
RESINT = internal reset;
LLC = line-locked clock output.
Fig 21. Power-on control circuit
9397 750 14232
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 9 May 2005
22 of 75
NXP [ NXP ]
