SAA7113H
Philips Semiconductors
9-bit video input processor
Y
LUM
LUMINANCE CIRCUIT
WEIGHTING
AND
ADDING
STAGE
VARIABLE
BAND-PASS
FILTER
CHROMINANCE
TRAP
PREFILTER
PREF
BYPS
VBLB
BPSS0
BPSS1
PREF
APER0
APER1
VBLB
MATCHING
AMPLIFIER
PREFILTER
SYNC
CLOCK CIRCUIT
CLOCKS
MACROVISION
DETECTOR
COPRO
VBLB
LINE-LOCKED
CLOCK
GENERATOR
17
LLC
V
PHASE
DETECTOR
FINE
SYNC SLICER
PHASE
DETECTOR
COARSE
10
11
40
DDA0
CLOCK
GENERATION
CIRCUIT
V
DAC6
SYNCHRONIZATION CIRCUIT
SSA0
CE
AUFD
VNOI0
VNOI1
HSB[7:0]
HSS[7:0]
2
I C-BUS CONTROL
HPLL
HTC[1:0]
HTC[1:0]
HTC[1:0] FIDT
FSEL HLCK
INCS
32
31
DISCRETE
TIME
OSCILLATOR 2
CRYSTAL
CLOCK
GENERATOR
XTALI
XTAL
2
I C-BUS
LOOP FILTER
VERTICAL
PROCESSOR
COUNTER
INTERFACE
2
24 23
26
27
mhb329
RTS0
RTS1
SCL SDA
Fig 19. Luminance and sync processing
8.5 Synchronization
The prefiltered luminance signal is fed to the synchronization stage. Its bandwidth is
further reduced to 1 MHz in a low-pass filter. The sync pulses are sliced and fed to the
phase detectors where they are compared with the sub-divided clock frequency. The
resulting output signal is applied to the loop filter to accumulate all phase deviations.
Internal signals (e.g. HCL and HSY) are generated in accordance with analog front-end
requirements. The loop filter signal drives an oscillator to generate the line frequency
control signal LFCO (see Figure 19).
The detection of ‘pseudo syncs’ as part of the Macrovision copy protection standard is
also done within the synchronization circuit.
The result is reported as flag COPRO within the decoder status byte at subaddress 1Fh.
9397 750 14232
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 9 May 2005
20 of 75
NXP [ NXP ]
