SAA7113H
Philips Semiconductors
9-bit video input processor
The data type selections by LCR are overruled by setting VIPB (subaddress 11h, bit 1) to
logic 1. This setting is mainly intended for device production tests. The VPO-bus carries
the upper or lower 8 bits of the two ADCs depending on the ADLSB (subaddress 13h,
bit 7) setting. The output configuration is done via MODE3 to MODE0 settings
(subaddress 02h, bits 3 to 0; see Table 28). If the YC-mode is selected, the VPO-bus
carries the multiplexed output signals of both ADCs, in CVBS-mode the output of only one
ADC. No timing reference codes are generated in this mode.
Remark: The LSBs (bit 0) of the ADCs are available on pins RTS0 or RTS1.
See Section 9, subaddress 12h for details.
The SAV/EAV timing reference codes define start and end of valid data regions.
Table 8:
SAV/EAV format
Symbol Description
logic 1
Bit
7
6
F
field bit
1st field: F = 0
2nd field: F = 1
for vertical timing see Table 9 and Table 10
vertical blanking bit
5
V
VBI: V = 1
active video: V = 0
for vertical timing see Table 9 and Table 10
H = 0 in SAV; H = 1 in EAV
4
H
3 to 0
P[3:0]
reserved; evaluation not recommended (protection bits according to
ITU-R BT 656)
The generation of the H-bit and consequently the timing of SAV/EAV corresponds to the
selected data format. H = 0 during active data region. For all data formats excluding data
type 7 (raw data), the length of the active data region is 1440 LLC. For the YUV 4 : 2 : 2
formats (data types 15 and 6) every clock cycle within this range contains valid data
(see Table 16).
The sliced data stream (various standards, data types 0 to 5 and 8 to 14; see Table 20)
contains also invalid cycles marked as 00h.
The length of the raw data region (data type 7) is programmable via HSB7 to HSB0 and
HSS7 to HSS0 (subaddresses 06h and 07h; see Figure 24).
During horizontal blanking period between EAV and SAV the ITU-blanking code sequence
‘-80-10-80-10-...’ is transmitted.
The position of the F-bit is constant according to ITU-R BT 656 (see Table 9 and
Table 10).
The V-bit can be generated in four different ways (see Table 9 and Table 10) controlled via
OFTS1 and OFTS0 (subaddress 10h, bits 7 and 6), VRLN (subaddress 10h, bit 3) and
LCR2 to LCR24 (subaddresses 41h to 57h).
F and V bits change synchronously with the EAV code.
9397 750 14232
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 9 May 2005
26 of 75
NXP [ NXP ]
