SAA7113H
Philips Semiconductors
9-bit video input processor
8.6 Clock generation circuit
The internal CGC generates all clock signals required for the video input processor. The
internal signal LFCO is a digital-to-analog converted signal provided by the horizontal
PLL. It is the multiple of the line frequency: 6.75 MHz = 429 × fH (50 Hz) or
6.75 MHz = 432 × fH (60 Hz).
Internally the LFCO signal is multiplied by a factor of 2 and 4 in the PLL circuit (including
phase detector, loop filtering, VCO and frequency divider) to obtain the output clock
signals. The rectangular output clocks have a 50 % duty factor.
ZERO
CROSS
DETECTION
BAND PASS
FC = LLC/4
PHASE
DETECTION
LOOP
FILTER
LFCO
OSCILLATOR
LLC
DIVIDER
1/2
DIVIDER
1/2
LLC2
mhb330
Fig 20. Block diagram of clock generation circuit
Table 4:
Clock
XTAL
Clock frequencies
Frequency (MHz)
24.576
27
LLC
LLC2 (internal)
LLC4 (internal)
LLC8 (virtual)
13.5
6.75
3.375
9397 750 14232
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 9 May 2005
21 of 75
NXP [ NXP ]
