Philips Semiconductors
Product specification
9-bit video input processor
SAA7113H
15.2.27 SUBADDRESS 58H
Table 63 Framing code for programmable data types
SLICER SET (58H)
CONTROL BITS D7 TO D0
PROGRAMMABLE FRAMING CODE
(Default)
FC7 TO FC0
40H
15.2.28 SUBADDRESS 59H
Table 64 Horizontal offset
CONTROL BITS ADDRESS 5BH,
CONTROL BITS ADDRESS 59H,
DATA BITS D7 TO D0
SLICER SET (59H, 5BH)
HORIZONTAL OFFSET
DATA BITS D2 TO D0
HOFF10 TO HOFF8
HOFF7 TO HOFF0
Recommended value
3H
54H
15.2.29 SUBADDRESS 5AH
Table 65 Vertical offset
CONTROL BITS ADDRESS 5AH,
DATA BITS D7 TO D0
SLICER SET (5AH, 5BH)
CONTROL BIT 5BH, D4
VERTICAL OFFSET
Minimum value 0
VOFF8
VOFF7 TO VOFF0
0
1
0
0
0H
Maximum value 312
38H
07H
0AH
Value for 50 Hz 625 lines input
Value for 60 Hz 525 lines input
15.2.30 SUBADDRESS 5BH
Table 66 Field offset, MSBs for vertical and horizontal offsets
SLICER SET (5BH)
CONTROL BIT D7
FOFF
FIELD OFFSET
No modification of internal field indicator
0
1
Invert field indicator (even/odd; default)
15.2.31 SUBADDRESS 5EH
Table 67 SDID codes
SLICER SET (5EH)
SDID codes
D5
D4
D3
D2
D1
D0
SDID5
0
SDID4
0
SDID3
0
SDID2
0
SDID1
0
SDID0
0
SDID5 to SDID0 = 0H (default)
1999 Jul 01
71
NXP [ NXP ]
