Philips Semiconductors
Product specification
9-bit video input processor
SAA7113H
15.2.26 SUBADDRESS 41H TO 57H
Table 61 LCR register 2 to 24 (41H to 57H); see Table 4
D7 TO D4
D3 TO D0
LCR REGISTER 2 TO 24 (41H TO 57H)
FRAMING CODE
DT3 TO DT0(1) DT3 TO DT0(1)
WST625
CC625
VPS
teletext EuroWST, CCST
European closed caption
video programming service
wide screen signalling bits
US teletext (WST)
27H
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
001
9951H
WSS
1E3C1FH
WST525
CC525
Test line
Intercast
27H
US closed caption (line 21)
video component signal, VBI region
oversampled CVBS data
001
−
−
General text teletext
programmable
VITC625
VITC/EBU time codes (Europe)
programmable
VITC/SMPTE time codes (USA)
reserved
programmable
Reserved
NABTS
Japtext
JFS
−
US NABTS
−
programmable (A7H)
programmable
−
MOJI (Japanese)
Japanese format switch (L20/22)
Active video video component signal, active video
region (default)
Note
1. The assignment of the upper and lower nibbles to the corresponding field depends on the setting of FOFF
(subaddress 5B, D7); see Table 62.
Table 62 Setting of FOFF
FOFF
D7 TO D4
field 1
D3 TO D0
field 2
0
1
field 2
field 1
1999 Jul 01
70
NXP [ NXP ]
