Philips Semiconductors
Product specification
9-bit video input processor
SAA7113H
16 I2C-BUS START SET-UP
The given values force the following behaviour of the SAA7113H:
• The analog input AI11 expects a signal in CVBS format; analog anti-alias filter and AGC active
• Automatic field detection enabled, PAL BDGHI or NTSC M standard expected
• Standard ITU 656 output format enabled, VBI-data slicer disabled; see Table 74 note 2
• Contrast, brightness and saturation control in accordance with ITU standards
• Chrominance processing with nominal bandwidth (800 kHz).
Table 74 I2C-bus start set-up values
VALUES (BIN)
(HEX)
SUB
(HEX)
FUNCTION
chip version
NAME(1)
7
6
5
4
3
2
1
0
START
00
01
02
ID07 to ID00
read only
increment delay
X, X, X, X, IDEL
0
1
0
1
0
0
0
0
1
0
0
0
0
0
0
0
08
analog input control 1
FUSE1 and FUSE0, GUDL1 to GUDL0,
MODE3 to MODE0
C0
03
analog input control 2
X, HLNRS, VBSL, WPOFF, HOLDG,
GAFIX, GAI28 and GAI18
0
0
1
1
0
0
1
1
33
04
05
06
07
08
analog input control 3
analog input control 4
horizontal sync start
horizontal sync stop
sync control
GAI17 to GAI10
GAI27 to GAI20
HSB7 to HSB0
HSS7 to HSS0
0
0
1
0
1
0
0
1
0
0
0
0
1
0
0
0
0
0
0
1
0
0
1
1
1
0
0
0
1
0
0
0
0
0
0
0
0
1
1
0
00
00
E9
0D
98
AUFD, FSEL, FOET, HTC1, HTC0,
HPLL, VNOI1 and VNOI0
09
luminance control
BYPS, PREF, BPSS1 and BPSS0, VBLB,
UPTCV, APER1 and APER0
0
0
0
0
0
0
0
1
01
0A
0B
0C
0D
luminance brightness
luminance contrast
BRIG7 to BRIG0
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
80
47
40
00
CONT7 to CONT0
chrominance saturation SATN7 to SATN0
chrominance hue
control
HUEC7 to HUEC0
0E
0F
10
chrominance control
CDTO, CSTD2 to CSTD0, DCCF, FCTC,
CHBW1 and CHBW0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
1
0
0
01
2A
00
chrominance gain
control
ACGC, CGAIN6 to CGAIN0
format/delay control
OFTS1 and OFTS0,
HDEL1 and HDEL0, VRLN,
YDEL2 to YDEL0
11
output control 1
GPSW1, CM99, GPSW0, HLSEL, OEYC,
OERT, VIPB and COLO
0
0
0
0
1
1
0
0
0C
12
13
output control 2
output control 3
RTSE13 to RTSE10, RTSE03 to RTSE00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
01
00
ADLSB, X, X, OLDSB, FIDP, X,
AOSL1 and AOSL0
14
reserved
0
0
0
0
0
0
0
0
00
1999 Jul 01
73
NXP [ NXP ]
