Philips Semiconductors
Product specification
Video Input Processor (VIP)
SAA7111
PINS
SYMBOL
PLCC68
RES
32
QFP64
23
O
Reset output (active LOW); sets the device into a defined state.
All data outputs are in high impedance state. The I
2
C-bus is reset
(waiting for start condition) note 4.
Chip enable; connection to ground forces a reset.
Positive digital supply voltage 4 (+5 V).
Digital ground for positive supply voltage 4.
Not connected.
Not connected.
Horizontal sync output signal (programmable); the positions of the
positive and negative slopes are programmable in 8 LLC increments
over a complete line (equals 64
µs)
via I
2
C-bus bytes HSB and HSS.
Fine position adjustment in 2 LLC increments can be performed via
I
2
C-bits HDEL1 and HDEL0.
Two functions output; controlled by I
2
C-bit RTSE1.
RTSE1 = 0: PAL line identifier (LOW = PAL line); indicates the
inverted and non-inverted R
−
Y component for PAL signals.
RTSE1 = 1: H-PLL locked indicator; a high state indicates that the
internal horizontal PLL has locked.
Two functions output; controlled by I
2
C-bit RTSE0.
RTSE0 = 0: odd/even field identification (HIGH = odd field).
RTSE0 = 1: vertical locked indicator; a HIGH state indicates that the
internal VNL has locked.
Vertical sync output signal (enabled via I
2
C-bit OEHV); this signal
indicates the vertical sync with respect to the YUV output. The HIGH
period of this signal is approximately six lines if the vertical noise
limiter (VNL) function is active. The positive slope contains the phase
information for a deflection controller.
Horizontal reference output signal (enabled via I
2
C-bit OEHV); this
signal is used to indicate data on the digital YUV bus. The positive
slope marks the beginning of a new active line. The HIGH period of
HREF is 720 Y samples long. HREF can be used to synchronize data
multiplexer/demultiplexers. HREF is also present during the vertical
blanking interval.
Digital ground for positive supply voltage 3.
Positive digital supply voltage 3 (+5 V).
Digital VPO-bus (Video Port Out) output signal; higher bits of the
16-bit YUV-bus or the 16-bit RGB-bus output signal. The output data
rate, the format and multiplexing scheme of the VPO-bus are
controlled via I
2
C-bits OFTS0 and OFTS1. With I
2
C-bit VIPB = 1 the
six MSBs of the digitized input signal (AD1 [7 to 2]) are connected to
these outputs.
Digital ground for positive supply voltage 2.
Positive digital supply voltage 2 (+5 V).
I/O
DESCRIPTION
CE
V
DD4
V
SS4
n.c.
n.c.
HS
33
34
35
36
37
38
24
25
26
−
−
27
I
P
GND
−
−
O
RTS1
39
28
O
RTS0
40
29
O
VS
41
30
O
HREF
42
31
O
V
SS3
V
DD3
VPO (15 to 10)
43
44
45 to 50
32
33
34 to 39
GND
P
O
V
SS2
V
DD2
51
52
40
41
GND
P
1998 May 15
7
PHILIPS [ NXP SEMICONDUCTORS ]
