欢迎访问ic37.com |
会员登录 免费注册
发布采购

SAA7111WP 参数 Datasheet PDF下载

SAA7111WP图片预览
型号: SAA7111WP
PDF下载: 下载PDF文件 查看货源
内容描述: 视频输入处理器VIP [Video Input Processor VIP]
分类和应用:
文件页数/大小: 64 页 / 406 K
品牌: PHILIPS [ NXP SEMICONDUCTORS ]
 浏览型号SAA7111WP的Datasheet PDF文件第7页浏览型号SAA7111WP的Datasheet PDF文件第8页浏览型号SAA7111WP的Datasheet PDF文件第9页浏览型号SAA7111WP的Datasheet PDF文件第10页浏览型号SAA7111WP的Datasheet PDF文件第12页浏览型号SAA7111WP的Datasheet PDF文件第13页浏览型号SAA7111WP的Datasheet PDF文件第14页浏览型号SAA7111WP的Datasheet PDF文件第15页  
Philips Semiconductors
Product specification
Video Input Processor (VIP)
8
8.1
FUNCTIONAL DESCRIPTION
Analog input processing
SAA7111
control (AGC) as part of the Analog Input Control (AICO).
The AGC (automatic gain control for luminance) is used to
amplify a CVBS or Y signal to the required signal
amplitude, matched to the ADCs input voltage range.
The AGC active time is the sync bottom of the video signal.
The SAA7111 offers four analog signal inputs, two analog
main channels with clamp circuit, analog amplifier,
anti-alias filter and video CMOS ADC (see Fig.6).
8.2
Analog control circuits
The anti-alias filters are adapted to the line-locked clock
frequency with help from a filter control. During the vertical
blanking, time gain and clamping control are frozen.
8.2.1
C
LAMPING
handbook, halfpage
analog input level
+4
dB
0 dB
(1 V(p-p) 75
Ω)
−6
dB
maximum
controlled
ADC input level
The clamp control circuit controls the correct clamping of
the analog input signals. The coupling capacitor is also
used to store and filter the clamping voltage. An internal
digital clamp comparator generates the information with
respect to clamp-up or clamp-down. The clamping levels
for the two ADC channels are fixed for luminance (60) and
chrominance (128). Clamping time in normal use is set
with the HCL pulse at the back porch of the video signal.
range 10 dB
0 dB
minimum
MGC660
Fig.5 Automatic gain range.
8.3
handbook, halfpage
Chrominance processing
TV line
analog line blanking
225
GAIN
60
1
CLAMP
HCL
HSY
MGC661
The 8-bit chrominance signal is fed to the multiplication
inputs of a quadrature demodulator, where two subcarrier
signals from the local oscillator DTO1 are applied
(0 and 90° phase relationship to the demodulator axis).
The frequency is dependent on the present colour
standard. The output signals of the multipliers are
low-pass filtered (four programmable characteristics) to
achieve the desired bandwidth for the colour difference
signals.
The colour difference signals are fed to the
Brightness/Contrast/Saturation block (BCS), which
includes the following five functions;
1. AGC (automatic gain control for chrominance)
2. Chroma amplitude matching [different gain factors for
(R−Y) and (B−Y) to achieve CCIR-601 levels
Cr and Cb]
3. Chroma saturation control
4. Luminance contrast and brightness
5. Limiting YUV to the values 1 (min.) and 254 (max.) to
fulfil CCIR-601 requirements.
Fig.4
Analog line with clamp (HCL) and gain
range (HSY).
8.2.2
G
AIN CONTROL
Signal (white) peak control limits the gain at signal
overshoots. The flow charts (see Figs 10 and 11) show
more details of the AGC. The influence of supply voltage
variation within the specified range is automatically
eliminated by clamp and automatic gain control.
The gain control circuit receives (via the I
2
C-bus) the static
gain levels for the two analog amplifiers or controls one of
these amplifiers automatically via a built-in automatic gain
1998 May 15
11