Philips Semiconductors
Product specification
Video Input Processor (VIP)
Fast enable is achieved by setting input FEI to LOW.
The signal is used to control fast switching on the digital
VPO-bus. HIGH on this pin forces the YUV outputs to a
high-impedance state (see Figs 15 and 17).
The digitized analog PAL or NTSC signals AD1 (7 to 0)
and AD2 (7 to 0) are connected directly to the VPO-bus
via I
2
C-bit VIPB = 1.
AD1 (7 to 0)
→
VPO (15 to 8) and
AD2 (7 to 0)
→
VPO (7 to 0)
The selection of the analog input channels are controlled
via I
2
C-bus subaddress 02 MODE select.
8.7
Synchronization
SAA7111
It is possible to force a reset by pulling the CE
(chip enable) to ground. After the rising edge of CE and
sufficient power supply voltage, the outputs LLC, LLC2,
CREF, RTCO, RTS0, RTS1, GPSW and SDA return from
3-state to active, while HREF, VREF, HS and VS remain in
3-state and have to be activated via I
2
C-bus programming
(see Table 4).
8.10
RTCO output
The prefiltered luminance signal is fed to the
synchronization stage. Its bandwidth is reduced to 1 MHz
in a low-pass filter. The sync pulses are sliced and fed to
the phase detectors where they are compared with the
sub-divided clock frequency. The resulting output signal is
applied to the loop filter to accumulate all phase
deviations. Internal signals (e.g. HCL and HSY) are
generated in accordance with analog front-end
requirements. The output signals HS, VS, and PLIN are
locked to the timing reference, guaranteed between the
input signal and the HREF signal, as further improvements
to the circuit may change the total processing delay. It is
therefore not recommended to use them for applications
which require absolute timing accuracy on the input
signals. The loop filter signal drives an oscillator to
generate the line frequency control signal LFCO
(see Fig.8).
8.8
Clock generation circuit
The real time control and status output signal contains
serial information about the actual system clock
(increment of the HPLL), subcarrier frequency [increment
and phase (via reset) of the FSC-PLL] and PAL sequence
bit. The signal can be used for various applications in
external circuits, e.g. in a digital encoder to achieve clean
encoding (see Fig.16).
8.11
The Line-21 text slicer
The text slicer block detects and acquires Line-21 closed
captioning data from a 525-line CVBS signal. Extended
data services on Line-21 Field 2 are also supported.
If valid data is detected the two data bytes are stored in two
I
2
C-bus registers. A parity check is also performed and the
result is stored in the MSB of the corresponding byte.
A third I
2
C-bus register is provided for data valid and data
ready flags. The two bits F1VAL and F2VAL indicate that
the input signal carries valid Closed Captioning data on the
corresponding fields. The data ready bits F1RDY and
F2RDY have to be evaluated if asynchronous I
2
C-bus
reading is used.
8.11.1
S
UGGESTIONS FOR
I
2
C-
BUS INTERFACE OF THE
DISPLAY SOFTWARE READING LINE
-21
DATA
The internal CGC generates all clock signals required for
the video input processor. The internal signal LFCO is a
digital-to-analog converted signal provided by the
horizontal PLL. It is the multiple of the line frequency
(6.75 MHz = 432
×
f
h
). Internally the LFCO signal is
multiplied by a factor of 2 or 4 in the PLL circuit (including
phase detector, loop filtering, VCO and frequency divider)
to obtain the LLC and LLC2 output clock signals.
The rectangular output clocks have a 50% duty factor
(see Fig.22).
8.9
Power-on reset and CE input
There are two methods by which the software can acquire
the data;
1. Synchronous reading once per frame (or once per
field): It can use either the rising edge (Line-21 Field 1)
or both edges (Line-21 Field 1 or 2) of the ODD signal
(pin RTSO) to initiate an I
2
C-bus read transfer of the
three registers 1A, 1B and 1C
2. Asynchronous reading: It can poll either the F1RDY bit
(Line-21 Field 1) or both F1RDY/F2RDY bits (Line-21
Field 1 or 2). After valid data has been read the
corresponding F*RDY bit is set to LOW until new data
has arrived. The polling frequency has to be slightly
higher than the frame or field frequency, respectively.
A missing clock, insufficient digital or analog V
DDA0
supply
voltages (below 3.5 V) will initiate the reset sequence; all
outputs are forced to 3-state. The indicator output RES is
LOW for approximately 128 LLC after the internal reset
and can be applied to reset other circuits of the digital TV
system.
1998 May 15
13
PHILIPS [ NXP SEMICONDUCTORS ]
