Philips Semiconductors
Product specification
1GHz low-voltage Fractional-N synthesizer
SA7025
Test Pin
MAIN
DIVIDER
The Test pin, Pin 19, is a buffered logic input which is exclusively
ORed with the output of the prescaler. The output of the XOR gate
is the input to the MAIN divider. The Test pin must be connected to
REF
SM
DIVIDER
V
DD
during normal operation as a synthesizer. This pin can be used
as an input for verifying the divide ratio of the MAIN divider; while in
this condition the input to the prescaler, RF , may be connected to
AUX
DIVIDER
IN
V
CCP
through a 10kΩ resistor in order to place prescaler output into
a known state.
φ
MAIN
φ
AUX
T1
T0
SELECT
LOGIC
LOCK
SR00609
Figure 10. Test Mode Diagram
PIN FUNCTIONS
PIN
PIN
PIN
PIN
DC V
EQUIVALENT CIRCUIT
DC V
EQUIVALENT CIRCUIT
No. MNEMONIC
No. MNEMONIC
V
= 3V
DDA
V
1
2
CLOCK
DATA
––
9
RA
RN
1.35
DD
––
16
1.35
1.35
1
3
STROBE
TEST
––
––
9
25µA
19
17
RF
V
SS
V
SSA
V
= 3V
CCP
V
11
13
PHA
PHI
––
––
DDA
5
6
RF
2.1
2.1
IN
IN
5
6
11
2.5k
RF
2.5k
14
PHP
––
V
V
SSA
DD
V
SS
V
= 3V
DDA
8
REF
1.8
1.8
IN
IN
ENABLE
18
LOCK
––
10
18
100k
10
AUX
V
SS
V
SS
SR00610
Figure 11. Pin Functions
15
1996 Aug 6
NXP [ NXP ]
