PCF8583
NXP Semiconductors
Clock and calendar with 240 x 8-bit RAM
8.2 I2C-bus protocol
8.2.1 Addressing
Before any data is transmitted on the I2C-bus, the device which must respond is
addressed first. The addressing is always carried out with the first byte transmitted after
the start procedure.
The clock and calendar acts as a slave receiver or slave transmitter. The clock signal SCL
is only an input signal but the data signal SDA is a bidirectional line.
The clock and calendar slave address is shown in Table 5. Bit A0 corresponds to
hardware address pin A0. Connecting this pin to VDD or VSS allows the device to have one
of two different addresses.
Table 5.
I2C slave address byte
Slave address
Bit
7
6
5
4
3
2
1
0
MSB
LSB
R/W
1
0
1
0
0
0
A0
8.2.2 Clock and calendar READ or WRITE cycles
The I2C-bus configuration for the different PCF8583 READ and WRITE cycles is shown in
Figure 18, Figure 19 and Figure 20.
acknowledgement
from slave
acknowledgement
from slave
acknowledgement
from slave
S
SLAVE ADDRESS
0
A
REGISTER ADDRESS
A
DATA
A
P
R/W
n bytes
auto increment
memory register address
013aaa346
Fig 18. Master transmits to slave receiver (WRITE mode)
PCF8583
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 06 — 6 October 2010
17 of 37
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