PCF8583
NXP Semiconductors
Clock and calendar with 240 x 8-bit RAM
In the 50 Hz clock mode or event-counter mode the oscillator is disabled and the oscillator
input is switched to a high-impedance state. This allows the user to feed the 50 Hz
reference frequency or an external high speed event signal into the input OSCI.
7.11 Initialization
When power-on occurs the I2C-bus interface, the control and status register and all clock
counters are reset. The device starts time-keeping in the 32.768 kHz clock mode with the
24 hour format on the first of January at 0.00.00:00. A 1 Hz square wave with 50 % duty
cycle appears at the interrupt output pin (starts HIGH).
The stop counting flag of the control and status register must be set before loading the
actual time into the counters. Loading of illegal states leads to a temporary clock
malfunction.
PCF8583
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 06 — 6 October 2010
14 of 37
NXP [ NXP ]
