PCF8583
NXP Semiconductors
Clock and calendar with 240 x 8-bit RAM
8. Characteristics of the I2C-bus
8.1 Characteristics
The I2C-bus is for bidirectional, two-line communication between different ICs or modules.
The two lines are a Serial DAta line (SDA) and a Serial Clock Line (SCL). Both lines must
be connected to a positive supply via a pull-up resistor. Data transfer is initiated only when
the bus is not busy.
8.1.1 Bit transfer
One data bit is transferred during each clock pulse (see Figure 14). The data on the SDA
line must remain stable during the HIGH period of the clock pulse as changes in the data
line at this time are interpreted as a control signal.
SDA
SCL
data line
stable;
data valid
change
of data
allowed
mbc621
Fig 14. Bit transfer
8.1.2 Start and stop conditions
Both data and clock lines remain HIGH when the bus is not busy.
A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START
condition - S.
A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition - P (see Figure 15).
SDA
SCL
SDA
SCL
S
P
START condition
STOP condition
mbc622
Fig 15. Definition of start and stop conditions
8.1.3 System configuration
A device generating a message is a transmitter; a device receiving a message is the
receiver (see Figure 16). The device that controls the message is the master; and the
devices which are controlled by the master are the slaves.
PCF8583
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 06 — 6 October 2010
15 of 37
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