PCF8566
NXP Semiconductors
Universal LCD driver for low multiplex rates
Table 22. Bonding pad description
All x/y coordinates represent the position of the center of each pad with respect to the center
(x/y = 0) of the chip (see Figure 31).
Symbol
SDA
SCL
SYNC
CLK
VDD
OSC
A0
Pad
1
X (µm)
200
Y (µm)
−1235
−1235
−1235
−1235
−1235
−1235
−825
−625
−425
−225
−25
Description
I2C-bus data input / output
I2C-bus clock input / output
cascade synchronization input / output
external clock input / output
supply voltage
2
400
3
604
4
856
5
1062
1080
1080
1080
1080
1080
1080
1080
1080
1080
1080
1074
874
6
oscillator select
I2C-bus subaddress input
7
A1
8
A2
9
SA0
VSS
VLCD
BP0
BP2
BP1
BP3
S0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
I2C-bus slave address bit 0 input
logic ground
347
LCD supply voltage
547
LCD backplane output
747
947
1235
1235
1235
1235
1235
1235
1235
1235
1235
1235
765
LCD segment output
S1
674
S2
474
S3
274
S4
−274
−474
−674
−874
−1074
−1080
−1080
−1080
−1080
−1080
−1080
−1080
−1080
−1080
−1080
−1056
−830
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
565
365
165
−35
−235
−435
−635
−835
−1035
−1235
−1235
PCF8566_7
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 07 — 25 February 2009
40 of 48
NXP [ NXP ]
