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PCA9675PW,112 参数 Datasheet PDF下载

PCA9675PW,112图片预览
型号: PCA9675PW,112
PDF下载: 下载PDF文件 查看货源
内容描述: [PCA9675 - Remote 16-bit I/O expander for Fm+ I2C-bus with interrupt TSSOP2 24-Pin]
分类和应用: PC光电二极管外围集成电路
文件页数/大小: 34 页 / 276 K
品牌: NXP [ NXP ]
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PCA9675  
NXP Semiconductors  
Remote 16-bit I/O expander for Fm+ I2C-bus with interrupt  
12. Static characteristics  
Table 5.  
Static characteristics  
VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb = 40 C to +85 C; unless otherwise specified.  
Symbol Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
Supplies  
VDD  
supply voltage  
supply current  
2.3  
-
-
5.5  
V
IDD  
Operating mode; no load;  
250  
500  
A  
VI = VDD or VSS; fSCL = 1 MHz  
Istb  
standby current  
Standby mode; no load;  
VI = VDD or VSS  
-
-
2.5  
1.6  
10  
A  
[1]  
VPOR  
power-on reset voltage  
2.0  
V
Input SCL; input/output SDA  
VIL  
VIH  
IOL  
IL  
LOW-level input voltage  
HIGH-level input voltage  
LOW-level output current  
leakage current  
0.5  
0.7VDD  
20  
-
+0.3VDD  
V
-
5.5  
-
V
VOL = 0.4 V  
VI = VDD or VSS  
VI = VSS  
-
mA  
A  
pF  
1  
-
+1  
10  
Ci  
input capacitance  
-
5
I/Os; P00 to P07 and P10 to P17  
[2]  
[2]  
[2]  
[2]  
IOL  
LOW-level output current  
VOL = 0.5 V; VDD = 2.3 V  
VOL = 0.5 V; VDD = 3.0 V  
VOL = 0.5 V; VDD = 4.5 V  
VOL = 0.5 V; VDD = 4.5 V  
VOH = VSS  
12  
17  
25  
-
28  
35  
42  
-
-
mA  
mA  
mA  
mA  
A  
-
-
IOL(tot)  
IOH  
Itrt(pu)  
Cio(off)  
total LOW-level output current  
HIGH-level output current  
400  
300  
-
30  
0.5  
-
102  
1.0  
9
transient boosted pull-up current VOH = VSS; see Figure 14  
mA  
pF  
[3]  
off-state input/output  
capacitance  
10  
Interrupt INT  
IOL  
Co  
LOW-level output current  
output capacitance  
VOL = 0.4 V  
6
-
-
-
mA  
pF  
2.1  
5
Inputs AD0, AD1, AD2  
VIL  
VIH  
ILI  
LOW-level input voltage  
0.5  
0.7VDD  
1  
-
+0.3VDD  
V
HIGH-level input voltage  
input leakage current  
input capacitance  
-
5.5  
+1  
5
V
-
A  
pF  
Ci  
-
2.4  
[1] The power-on reset circuit resets the I2C-bus logic with VDD < VPOR and set all I/Os to logic 1 (with current source to VDD).  
[2] Each bit must be limited to a maximum of 25 mA and the total package limited to 400 mA due to internal busing limits.  
[3] The value is not tested, but verified on sampling basis.  
PCA9675  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 2 — 3 October 2011  
21 of 34  
 
 
 
 
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