Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM,
capture/compare, high I/O, low voltage (2.7V–5.5V), low power
P87C552
DC ELECTRICAL CHARACTERISTICS (Continued)
TEST
LIMITS
SYMBOL
PARAMETER
CONDITIONS
MIN
MAX
UNIT
Analog Inputs (Continued)
AV
AV
Analog input voltage
Reference voltage:
AV –0.2
AV +0.2
V
IN
SS
DD
REF
AV
AV
AV –0.2
V
V
REF–
REF+
SS
AV +0.2
DD
R
C
Resistance between AV
and AV
REF–
10
50
15
kΩ
pF
REF
REF+
Analog input capacitance
Sampling time (10 bit mode)
Sampling time (8 bit mode)
IA
t
t
t
t
8t
µs
ADS
ADS8
ADC
ADC8
CY
CY
5t
µs
Conversion time (including sampling time, 10 bit mode)
Conversion time (including sampling time, 8 bit mode)
50t
24t
µs
CY
µs
CY
10, 11, 12
DL
Differential non-linearity
±1
LSB
LSB
LSB
LSB
LSB
%
e
10, 13
IL
IL
Integral non-linearity
(10 bit mode)
±2
±1
e
Integral non-linearity (8 bit mode)
e8
10, 14
OS
OS
Offset error
(10 bit mode)
±2
e
Offset error (8 bit mode)
±1
e8
10, 15
G
Gain error
±0.4
±3
e
10, 16
A
e
Absolute voltage error
LSB
LSB
dB
M
CTC
Channel to channel matching
Crosstalk between inputs of port 5
±1
17, 18
C
0–100kHz
–60
t
NOTES FOR DC ELECTRICAL CHARACTERISTICS:
1. See Figures 57 through 60 for I test conditions, and Figure 56. Active mode: I (max) = (0.9 x FREQ. + 1.1) mA;
DD
DD
Idle Mode: I (max) = (0.18 x FREQ. + 1.01) mA.
ID
2. The operating supply current is measured with all output pins disconnected; XTAL1 driven with t = t = 10ns; V = V + 0.5V;
r
f
IL
SS
V
IH
= V – 0.5V; XTAL2 not connected; EA = RST = Port 0 = EW = V ; STADC = V
.
DD
DD
SS
3. The idle mode supply current is measured with all output pins disconnected; XTAL1 driven with t = t = 10ns; V = V + 0.5V;
r
f
IL
SS
V
IH
= V – 0.5V; XTAL2 not connected; Port 0 = EW = V ; EA = RST = STADC = V
.
DD
DD
SS
4. The power-down current is measured with all output pins disconnected; XTAL2 not connected; Port 0 = EW = V
;
DD
EA = RST = STADC = XTAL1 = V
.
SS
2
5. The input threshold voltage of P1.6 and P1.7 (SIO1) meets the I C specification, so an input voltage below 1.5V will be recognized as a logic
0 while an input voltage above 3.0V will be recognized as a logic 1.
6. Pins of ports 1 (except P1.6, P1.7), 2, 3, and 4 source a transition current when they are being externally driven from 1 to 0. The transition
current reaches its maximum value when V is approximately 2V.
IN
7. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V s of ALE and ports 1 and 3. The noise is due
OL
to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. I can exceed these conditions provided that no
OL
single output sinks more than 5mA and no more than two outputs exceed the test conditions.
8. Capacitive loading on ports 0 and 2 may cause the V on ALE and PSEN to momentarily fall below the 0.9V specification when the
OH
DD
address bits are stabilizing.
9. The following condition must not be exceeded: V – 0.2V < AV < V + 0.2V.
DD
DD
DD
10.Conditions: AV
= 0V; AV = 5.0V. Measurement by continuous conversion of AV = –20mV to 5.12V in steps of 0.5mV, derivating
REF–
DD
IN
parameters from collected conversion results of ADC. AV
= 4.977V. ADC is monotonic with no missing codes.
REF+
11. The differential non-linearity (DL ) is the difference between the actual step width and the ideal step width. (See Figure 47.)
e
12.The ADC is monotonic; there are no missing codes.
13.The integral non-linearity (IL ) is the peak difference between the center of the steps of the actual and the ideal transfer curve after
e
appropriate adjustment of gain and offset error. (See Figure 47.)
14.The offset error (OS ) is the absolute difference between the straight line which fits the actual transfer curve, and a straight line which fits the
e
ideal transfer curve. (See Figure 47.)
15.The gain error (G ) is the relative difference in percent between the straight line fitting the actual transfer curve (after removing offset error),
e
and the straight line which fits the ideal transfer curve. Gain error is constant at every point on the transfer curve. (See Figure 47.)
16.The absolute voltage error (A ) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated
e
ADC and the ideal transfer curve.
17.This should be considered when both analog and digital signals are simultaneously input to port 5.
18.This parameter is guaranteed by design and characterized, but is not production tested.
63
1999 Mar 30
NXP [ NXP ]
