Philips Semiconductors
Product data
Single-chip 8-bit microcontroller with 10-bit A/D,
capture/compare timer, high-speed outputs, PWM
80C552/83C552
AC ELECTRICAL CHARACTERISTICS (Continued)
SYMBOL
PARAMETER
INPUT
OUTPUT
2
I C Interface (Refer to Figure 9)
1
t
t
t
t
t
t
t
t
t
t
t
t
t
t
START condition hold time
≥ 14 t
> 4.0 µs
HD;STA
LOW
CLCL
CLCL
CLCL
1
SCL low time
≥ 16 t
≥ 14 t
> 4.7 µs
1
SCL high time
> 4.0 µs
HIGH
2
SCL rise time
≤ 1 µs
–
RC
3
SCL fall time
≤ 0.3 µs
≥ 250ns
≥ 250ns
≥ 250ns
≥ 0ns
< 0.3 µs
FC
Data set-up time
> 20 t
– t
SU;DAT1
SU;DAT2
SU;DAT3
HD;DAT
SU;STA
SU;STO
BUF
CLCL
RD
1
SDA set-up time (before rep. START cond.)
SDA set-up time (before STOP cond.)
Data hold time
> 1 µs
> 8 t
CLCL
> 8 t
– t
CLCL
FC
1
Repeated START set-up time
STOP condition set-up time
Bus free time
≥ 14 t
≥ 14 t
≥ 14 t
> 4.7 µs
> 4.0 µs
> 4.7 µs
CLCL
CLCL
CLCL
1
1
2
SDA rise time
≤ 1 µs
≤ 0.3 µs
–
RD
3
SDA fall time
< 0.3 µs
FD
NOTES:
1. At 100 kbit/s. At other bit rates this value is inversely proportional to the bit-rate of 100 kbit/s.
2. Determined by the external bus-line capacitance and the external bus-line pull-resistor, this must be < 1 µs.
3. Spikes on the SDA and SCL lines with a duration of less than 3 t
SCL = 400 pF.
will be filtered out. Maximum capacitance on bus-lines SDA and
CLCL
4. t
= 1/f
= one oscillator clock period at pin XTAL1. For 62 ns, 42 ns < t
< 285 ns (16 MHz, 24 MHz > f
> 3.5 MHz) the SI01
CLCL
OSC
CLCL
OSC
2
interface meets the I C-bus specification for bit-rates up to 100 kbit/s.
15
2002 Sep 03
NXP [ NXP ]
