Philips Semiconductors
Product data
Single-chip 8-bit microcontroller with 10-bit A/D,
capture/compare timer, high-speed outputs, PWM
80C552/83C552
1, 2
AC ELECTRICAL CHARACTERISTICS (Continued)
24 MHz version
24 MHz CLOCK
VARIABLE CLOCK
SYMBOL
1/t
FIGURE
PARAMETER
Oscillator frequency
MIN
MAX
MIN
MAX
UNIT
MHz
ns
2
2
2
2
2
2
2
2
2
2
2
2
3.5
24
CLCL
t
t
t
t
t
t
t
t
t
t
t
ALE pulse width
43
17
17
2t
–40
LHLL
CLCL
Address valid to ALE low
Address hold after ALE low
ALE low to valid instruction in
ALE low to PSEN low
t
–25
ns
AVLL
LLAX
LLIV
CLCL
CLCL
t
–25
ns
102
65
4t
3t
–65
ns
CLCL
17
80
t
–25
ns
LLPL
PLPH
PLIV
PXIX
PXIZ
AVIV
PLAZ
CLCL
PSEN pulse width
3t
–45
ns
CLCL
PSEN low to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address to valid instruction in
PSEN low to address float
–60
ns
CLCL
0
0
ns
17
128
10
t
–25
ns
CLCL
5t
–80
ns
CLCL
10
ns
Data Memory
t
t
t
t
t
t
t
t
t
t
t
t
t
t
3
4
RD pulse width
150
150
6t
–100
–100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RLRH
WLWH
RLDV
RHDX
RHDZ
LLDV
AVDV
LLWL
AVWL
QVWX
DW
CLCL
WR pulse width
6t
CLCL
3
RD low to valid data in
Data hold after RD
118
5t
2t
–90
–28
CLCL
3
0
0
3
Data float after RDxs
ALE low to valid data in
Address to valid data in
ALE low to RD or WR low
Address valid to WR low or RD low
Data valid to WR transition
Data before WR
55
CLCL
3
183
210
175
8t
–150
–165
CLCL
CLCL
3
9t
3, 4
3, 4
4
75
92
3t
–50
–75
3t
CLCL
+50
CLCL
4t
CLCL
12
t
CLCL
7t
CLCL
t
CLCL
–30
4
162
17
–130
–25
4
Data hold after WR
WHQX
RLAZ
WHLH
3
RD low to address float
RD or WR high to ALE high
0
0
3, 4
17
67
t
–25
t
+25
CLCL
CLCL
External Clock
3
t
t
t
t
5
5
5
5
High time
17
17
17
17
ns
ns
ns
ns
CHCX
CLCX
CLCH
CHCL
3
Low time
3
Rise time
5
5
20
20
3
Fall time
3
Serial Timing – Shift Register Mode (Test Conditions: T
= 0 °C to +70 °C; V = 0 V; Load Capacitance = 80 pF)
SS
amb
t
t
t
t
t
6
6
6
6
6
Serial port clock cycle time
0.5
283
23
0
12t
µs
ns
ns
ns
ns
XLXL
CLCL
Output data setup to clock rising edge
Output data hold after clock rising edge
Input data hold after clock rising edge
Clock rising edge to input data valid
10t
–133
–60
QVXH
XHQX
XHDX
XHDV
CLCL
2t
CLCL
0
283
10t
–133
CLCL
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF.
3. These values are characterized but not 100% production tested.
4. t
t
= 1/f
= 41.7ns at f
= one oscillator clock period.
CLCL
CLCL
OSC
= 24 MHz.
OSC
14
2002 Sep 03
NXP [ NXP ]
