Philips Semiconductors
Product data
Single-chip 8-bit microcontroller with 10-bit A/D,
capture/compare timer, high-speed outputs, PWM
80C552/83C552
1, 2
AC ELECTRICAL CHARACTERISTICS
16 MHz version
16 MHz CLOCK
VARIABLE CLOCK
SYMBOL
1/t
FIGURE
PARAMETER
Oscillator frequency
MIN
MAX
MIN
MAX
UNIT
MHz
ns
2
2
2
2
2
2
2
2
2
2
2
2
3.5
16
CLCL
t
t
t
t
t
t
t
t
t
t
t
ALE pulse width
85
8
2t
–40
LHLL
CLCL
Address valid to ALE low
Address hold after ALE low
ALE low to valid instruction in
ALE low to PSEN low
t
t
–55
ns
AVLL
LLAX
LLIV
CLCL
CLCL
28
–35
ns
150
83
4t
3t
–100
ns
CLCL
23
t
–40
ns
LLPL
PLPH
PLIV
PXIX
PXIZ
AVIV
PLAZ
CLCL
PSEN pulse width
143
3t
–45
ns
CLCL
PSEN low to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address to valid instruction in
PSEN low to address float
–105
ns
CLCL
0
0
ns
38
208
10
t
–25
ns
CLCL
5t
–105
ns
CLCL
10
ns
Data Memory
t
t
t
t
t
t
t
t
t
t
t
t
t
t
3
4
RD pulse width
275
275
6t
–100
–100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RLRH
WLWH
RLDV
RHDX
RHDZ
LLDV
AVDV
LLWL
AVWL
QVWX
DW
CLCL
WR pulse width
6t
CLCL
3
RD low to valid data in
Data hold after RD
148
5t
–165
CLCL
3
0
0
3
Data float after RD
55
2t
–70
CLCL
3
ALE low to valid data in
Address to valid data in
ALE low to RD or WR low
Address valid to WR low or RD low
Data valid to WR transition
Data before WR
350
398
238
8t
CLCL
9t
CLCL
–150
–165
3
3, 4
3, 4
4
138
120
3
3t
–50
3t
+50
CLCL
CLCL
4t
t
–130
–60
CLCL
CLCL
CLCL
CLCL
4
288
13
7t
t
–150
–50
4
Data hold after WR
WHQX
RLAZ
WHLH
3
RD low to address float
RD or WR high to ALE high
0
0
3, 4
23
103
t
–40
t
+40
CLCL
CLCL
External Clock
4
t
t
t
t
5
5
5
5
High time
20
20
20
20
ns
ns
ns
ns
CHCX
CLCX
CLCH
CHCL
4
Low time
4
Rise time
20
20
20
20
4
Fall time
4
Serial Timing – Shift Register Mode (Test Conditions: T
= 0 °C to +70 °C; V = 0 V; Load Capacitance = 80 pF)
SS
amb
t
t
t
t
t
6
6
6
6
6
Serial port clock cycle time
0.75
492
8
12t
µs
ns
ns
ns
ns
XLXL
CLCL
Output data setup to clock rising edge
Output data hold after clock rising edge
Input data hold after clock rising edge
Clock rising edge to input data valid
10t
–133
QVXH
XHQX
XHDX
XHDV
CLCL
2t
CLCL
–117
0
0
492
10t –133
CLCL
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF.
3. t
= 1/f
= 83.3ns at f
= 62.5ns at f
= one oscillator clock period.
CLCL
CLCL
CLCL
OSC
t
t
= 12 MHz.
= 16 MHz.
OSC
OSC
4. These values are characterized but not 100% production tested.
13
2002 Sep 03
NXP [ NXP ]
