Philips Semiconductors
Product data
Single-chip 8-bit microcontroller with 10-bit A/D,
capture/compare timer, high-speed outputs, PWM
80C552/83C552
DC ELECTRICAL CHARACTERISTICS (Continued)
TEST
CONDITIONS
LIMITS
SYMBOL
PARAMETER
MIN
MAX
UNIT
Analog Inputs
AI
DD
Analog supply current: operating: (16 MHz)
Analog supply current: operating: (24 MHz)
Port 5 = 0 to AV
Port 5 = 0 to AV
1.2
1.0
mA
mA
DD
DD
Idle mode:
AI
ID
P83(0)C552EBx
P83(0)C552EFx
P83(0)C552EHx
P83(0)C552IBx
P83(0)C552IFx
50
50
100
50
µA
µA
µA
µA
µA
50
Power-down mode:
2 V < AV < AV
AI
PD
PD
DD
max
P83(0)C552xBx
P83(0)C552xFx
P83(0)C552xHx
50
50
100
µA
µA
µA
AV
AV
Analog input voltage
Reference voltage:
AV –0.2
AV +0.2
V
IN
SS
DD
REF
AV
AV
AV –0.2
V
V
REF–
REF+
SS
AV +0.2
DD
R
C
Resistance between AV
and AV
REF–
10
50
15
kΩ
pF
REF
REF+
Analog input capacitance
Sampling time
IA
t
t
8t
CY
µs
ADS
ADC
Conversion time (including sampling time)
50t
µs
CY
10, 11, 12
DL
Differential non-linearity
±1
LSB
LSB
LSB
%
e
10, 13
IL
e
Integral non-linearity
±2
±2
10, 14
OS
Offset error
e
10, 15
G
Gain error
±0.4
±3
e
10, 16
A
e
Absolute voltage error
LSB
LSB
dB
M
CTC
Channel to channel matching
±1
17
C
Crosstalk between inputs of port 5
0–100kHz
–60
t
NOTES FOR DC ELECTRICAL CHARACTERISTICS:
1. See Figures 10 through 15 for I test conditions.
DD
2. The operating supply current is measured with all output pins disconnected; XTAL1 driven with t = t = 10 ns; V = V + 0.5 V;
r
f
IL
SS
V
IH
= V – 0.5 V; XTAL2 not connected; EA = RST = Port 0 = EW = V ; STADC = V
.
DD
DD
SS
3. The idle mode supply current is measured with all output pins disconnected; XTAL1 driven with t = t = 10 ns; V = V + 0.5 V;
r
f
IL
SS
V
IH
= V – 0.5 V; XTAL2 not connected; Port 0 = EW = V ; EA = RST = STADC = V
.
DD
DD
SS
4. The power-down current is measured with all output pins disconnected; XTAL2 not connected; Port 0 = EW = V
;
DD
EA = RST = STADC = XTAL1 = V
.
SS
2
5. The input threshold voltage of P1.6 and P1.7 (SIO1) meets the I C specification, so an input voltage below 1.5 V will be recognized as a
logic 0 while an input voltage above 3.0 V will be recognized as a logic 1.
6. Pins of ports 1 (except P1.6, P1.7), 2, 3, and 4 source a transition current when they are being externally driven from 1 to 0. The transition
current reaches its maximum value when V is approximately 2 V.
IN
7. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V s of ALE and ports 1 and 3. The noise is due
OL
to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100 pF), the noise pulse on the ALE pin may exceed 0.8 V. In such cases, it may be desirable to qualify
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. I can exceed these conditions provided that no
OL
single output sinks more than 5mA and no more than two outputs exceed the test conditions.
8. Capacitive loading on ports 0 and 2 may cause the V on ALE and PSEN to momentarily fall below the 0.9 V specification when the
OH
DD
address bits are stabilizing.
9. The following condition must not be exceeded: V – 0.2 V < AV < V + 0.2 V.
DD
DD
DD
10.Conditions: AV
= 0 V; AV = 5.0 V, AV
(80C552, 83C552) = 5.12 V. ADC is monotonic with no missing codes. Measurement by
REF–
DD
REF+
continuous conversion of AV = –20 mV to 5.12 V in steps of 0.5 mV.
IN
11. The differential non-linearity (DL ) is the difference between the actual step width and the ideal step width. (See Figure 1.)
e
12.The ADC is monotonic; there are no missing codes.
13.The integral non-linearity (IL ) is the peak difference between the center of the steps of the actual and the ideal transfer curve after
e
appropriate adjustment of gain and offset error. (See Figure 1.)
11
2002 Sep 03
NXP [ NXP ]
