LPC2131/32/34/36/38
NXP Semiconductors
Single-chip 16/32-bit microcontrollers
Table 4.
Interrupt sources …continued
Flag(s)
Block
VIC channel #
UART1
RX Line Status (RLS)
7
Transmit Holding Register empty (THRE)
RX Data Available (RDA)
Character Time-out Indicator (CTI)
Modem Status Interrupt (MSI) (Available in LPC2134/36/38
only)
PWM0
Match 0 to 6 (MR0, MR1, MR2, MR3, MR4, MR5, MR6)
Capture 0 to 3 (CR0, CR1, CR2, CR3)
SI (state change)
8
I2C0
SPI0
SSP
9
SPIF, MODF
10
11
TX FIFO at least half empty (TXRIS)
RX FIFO at least half full (RXRIS)
Receive Timeout (RTRIS)
Receive Overrun (RORRIS)
PLL
PLL Lock (PLOCK)
12
13
14
15
16
17
18
19
20
21
RTC
RTCCIF (Counter Increment), RTCALF (Alarm)
System Control External Interrupt 0 (EINT0)
External Interrupt 1 (EINT1)
External Interrupt 2 (EINT2)
External Interrupt 3 (EINT3)
AD0
I2C1
BOD
AD1
ADC 0
SI (state change)
Brown Out Detect
ADC 1 (Available in LPC2134/36/38 only)
6.6 Pin connect block
The pin connect block allows selected pins of the microcontroller to have more than one
function. Configuration registers control the multiplexers to allow connection between the
pin and the on chip peripherals. Peripherals should be connected to the appropriate pins
prior to being activated, and prior to any related interrupt(s) being enabled. Activity of any
enabled peripheral function that is not mapped to a related pin should be considered
undefined.
6.7 General purpose parallel I/O and Fast I/O
Device pins that are not connected to a specific peripheral function are controlled by the
GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate
registers allow setting or clearing any number of outputs simultaneously. The value of the
output register may be read back, as well as the current state of the port pins.
6.7.1 Features
• Direction control of individual bits.
• Separate control of output set and clear.
• All I/O default to inputs after reset.
LPC2131_32_34_36_38
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5.1 — 29 July 2011
16 of 45
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