ISP1581
Hi-Speed USB peripheral controller
Philips Semiconductors
RD/WR
CS
READY
t
004aaa152
RDY1
t
RDY2
Fig 13. ISP1581 READY signal timing.
Table 74: ISP1581 register access timing parameters: separate address and data buses
VCC = 4.0 to 5.5 V; VGND = 0 V; Tamb = −40 to +85 °C.
Symbol
Reading
tRLRH
Parameter
Min
Max
Unit
RD LOW pulse width
>tRLDV
-
ns
ns
ns
ns
ns
ns
tAVRL
address set-up time before RD LOW
address hold time after RD HIGH
RD LOW to data valid delay
0
0
-
-
tRHAX
-
tRLDV
26
15
-
tRHDZ
RD HIGH to data outputs three-state delay
RD HIGH to CS HIGH delay
0
0
tRHSH
Writing
tWLWH
tAVWL
WR LOW pulse width
15
0
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
address set-up time before WR LOW
address hold time after WR HIGH
data set-up time before WR HIGH
data hold time after WR HIGH
WR HIGH to CS HIGH delay
tWHAX
tDVWH
tWHDZ
tWHSH
General
Tcy(RW)
tI1VI2L
tI2HI1X
tRDY1
0
11
5
0
read/write cycle time
80
0
0
-
-
ns
ns
ns
ns
ns
R/W set-up time before DS LOW
R/W hold time after DS HIGH
-
-
READY LOW to CS LOW delay
READY HIGH to RD/WR HIGH of the last access
3
91
tRDY2
-
9397 750 13462
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 06 — 23 December 2004
54 of 79
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