ISP1362
Single-chip USB OTG controller
Philips Semiconductors
To give a better view of the functionality, Figure 15 shows a possible curve of VCC with
dips at t2–t3 and t4–t5. If the dip at t4–t5 is too short (that is, < 11 µs), the internal
POR pulse will not react and will remain LOW. The internal POR starts with a HIGH at
t0. At t1, the detector will see the passing of the trip level and a delay element will add
another tPORP before it drops to LOW.
The internal POR pulse will be generated whenever VCC drops below Vtrip for more
than 11 µs.
V
CC
V
trip
t4
t0
t1
t
t3
t5
t2
(1)
PORP
t
PORP
PORP
004aaa482
(1) PORP = power-on reset pulse.
Fig 15. Internal power-on reset timing.
The RESET pin can be either connected to VCC (using the internal POR circuit) or
externally controlled (by the micro, ASIC, and so on). Figure 16 shows the availability
of the clock with respect to the external reset pulse.
RESET
EXTERNAL CLOCK
004aaa484
A
Stable external clock is available at A.
Fig 16. Clock with respect to the external power-on reset.
11. On-The-Go (OTG) controller
11.1 Introduction
OTG is a supplement to the Hi-Speed USB (USB 2.0) specification that augments
existing USB peripherals by adding to these peripherals limited host capability to
support other targeted USB peripherals. It is primarily targeted at portable devices
because it addresses concerns related to such devices, such as a small connector
and low power. Non-portable devices (even standard hosts), nevertheless, can also
benefit from OTG features.
9397 750 12337
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 03 — 06 January 2004
31 of 150
NXP [ NXP ]
