ISP1362
Single-chip USB OTG controller
Philips Semiconductors
OtgInterruptEnable register
OTG_TMR_IE
B_SE0_SRP_IE
A_SRP_DET_IE
OTG_RESUME_IE
OTG_SUSPND_IE
RMT_CONN_IE
B_SESS_VLD_IE
A_SESS_VLD_IE
B_SESS_END_IE
OR
A_VBUS_VLD_IE
ID_REG_IE
OtgInterrupt register
OTG_TMR_TIMEOUT
B_SE0_SRP
level 2
A_SRP_DET
(OTG group)
OTG_RESUME
OTG_SUSPND
RMT_CONN_C
B_SESS_VLD_C
A_SESS_VLD_C
B_SESS_END_C
HcµPInterrupt register
HcµPInterruptEnable register
A_VBUS_VLD_C
ID_REG_C
HcInterruptEnable register
MIE
RHSC
FNO
UE
OR
RD
SF
SO
level 2
(OPR group)
HcInterruptStatus register
RHSC
FNO
UE
OR
level 1
RD
SF
SO
HcHardwareConfiguration register
InterruptPinEnable
004aaa395
LE
LATCH
INT1
From INT2
OneINT
HcHardwareConfiguration
register
Fig 14. HC and OTG interrupt logic.
9397 750 12337
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 03 — 06 January 2004
28 of 150
NXP [ NXP ]
