ISP1362
Single-chip USB OTG controller
Philips Semiconductors
• DcInterruptEnable
• DcInterrupt.
The DcMode register (bit 3) is the overall DC interrupt enable.
DcHardwareConfiguration determines the following features:
• Level-triggered or edge-triggered (bit 1)
• Output polarity (bit 0).
For details on the interrupt logic in the DC, refer to the Interrupt Control application
note.
9.7.3 Combining INT1 and INT2
In some embedded systems, interrupt inputs to the CPU are a very scarce resource.
The system designer might want to use just one interrupt line to serve the HC, the DC
and the OTG controller. In such a case, make sure the OneINT feature is activated.
When OneINT (bit 9 of the HcHardwareConfiguration register) is set to logic 1, both
the INT1 (HC or OTG controller) interrupt and the INT2 (DC) interrupt are routed to
pin INT1, thereby reducing hardware resource requirements.
Remark: Both the host controller (or OTG controller) and the device controller
interrupts must be set to the same polarity (active HIGH or active LOW) and the same
trigger type (edge or level). Failure to conform to this will lead to unpredictable
behavior of the ISP1362.
9.7.4 Behavior difference between level-triggered and edge-triggered interrupts
In many microprocessor systems, the operating system disables an interrupt when it
is in an Interrupt Service Routine (ISR). If there is an interrupt event during this
period, it will lead to:
Level-triggered interrupt: When the ISP1362 interrupt asserts, the operating
system takes no action because it disables the interrupt when it is in the ISR. The
interrupt line of the ISP1362 remains asserted. When the operating system exits the
ISR and re-enables the interrupt processing, it sees the asserted interrupt line and
immediately enters the ISR.
Edge-triggered interrupt: When the ISP1362 outputs a pulse, the operating system
takes no action because it disables the interrupt when it is in the ISR. The interrupt
line of the ISP1362 goes back to the inactive state. When the operating system exits
the ISR and re-enables the interrupt processing, it sees no pending interrupt. As a
result, the interrupt is missed.
If the system needs to know whether an interrupt (approximately 160 ns pulse width)
occurs during this period, it may read the HcµPInterrupt register (see Table 68).
10. Power-on reset (POR)
When VCC is directly connected to the RESET pin, the internal POR pulse width
(tPORP) will be typically 800 ns. The pulse is started when VCC rises above Vtrip
(2.03 V).
9397 750 12337
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 03 — 06 January 2004
30 of 150
NXP [ NXP ]
