ISP1362
Single-chip USB OTG controller
Philips Semiconductors
• HcµPInterrupt
– Before initiating the DMA transfer, clear AllEOTInterrupt (bit 3). This bit is set
when the DMA transfer is complete.
• HcTransferCounter
– If DMACounterEnable of the HcDMAConfiguration register is set (that is, the
DMA counter is enabled), HcTransferCounter must be set to the number of
bytes to be transferred.
• HcDMAConfiguration
– Read or write DMA (bit 0)
– Targeted buffer: ISTL0, ISTL1, ATL and INTL (bits 1 to 3)
– DMA enable or disable (bit 4)
– Burst length (bits 5 to 6)
– DMA counter enable (bit 7).
Remark: Configure the HcDMAConfiguration register only after you have configured
all the other registers. The ISP1362 will assert DREQ1 once the DMA enable bit in
this register is set.
9.6.2 Combining the two DMA channels
The ISP1362 allows systems with limited DMA channels to use a single DMA channel
(DMA1) for both the HC and the DC. This option can be enabled by writing logic 1 to
the OneDMA bit of the HcHardwareConfiguration register. If this option is enabled,
the polarity of the DC DMA and the HC DMA must be set to DACK active LOW and
DREQ active HIGH.
9.7 Interrupts
Various events in the HC, the DC and the OTG controller can be programmed to
generate a hardware interrupt. By default, the interrupt generated by the HC and the
OTG controller is routed out at the INT1 pin and the interrupt generated by the DC is
routed out at the INT2 pin.
9.7.1 Interrupt in the HC and the OTG controller
There are two levels of interrupts represented by level 1 and level 2 (see Figure 14).
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© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 03 — 06 January 2004
27 of 150
NXP [ NXP ]
