ISP1160
Embedded USB Host Controller
Philips Semiconductors
Contents
1
2
3
4
5
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
17.2
DMA timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 76
18
18.1
18.2
Application information . . . . . . . . . . . . . . . . . 79
Typical interface circuit . . . . . . . . . . . . . . . . . . 79
Interfacing a ISP1160 to a SH7709
RISC processor. . . . . . . . . . . . . . . . . . . . . . . 79
Typical software model. . . . . . . . . . . . . . . . . . 80
18.3
19
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Test information. . . . . . . . . . . . . . . . . . . . . . . . 81
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 82
20
21
21.1
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Introduction to soldering surface mount
packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 84
Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 84
Manual soldering . . . . . . . . . . . . . . . . . . . . . . 85
Package related soldering information. . . . . . 85
7
Functional description . . . . . . . . . . . . . . . . . . . 8
PLL clock multiplier. . . . . . . . . . . . . . . . . . . . . . 8
Bit clock recovery . . . . . . . . . . . . . . . . . . . . . . . 8
Analog transceivers . . . . . . . . . . . . . . . . . . . . . 8
Philips Serial Interface Engine (SIE). . . . . . . . . 8
7.1
7.2
7.3
7.4
21.2
21.3
21.4
21.5
8
Microprocessor bus interface. . . . . . . . . . . . . . 8
Programmed I/O (PIO) addressing mode. . . . . 8
DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Control registers access by PIO mode . . . . . . 10
FIFO buffer RAM access by PIO mode . . . . . 11
FIFO buffer RAM access by DMA mode. . . . . 12
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
8.1
8.2
8.3
8.4
8.5
8.6
22
23
24
25
26
Revision history . . . . . . . . . . . . . . . . . . . . . . . 86
Data sheet status. . . . . . . . . . . . . . . . . . . . . . . 87
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
9
Host Controller (HC) . . . . . . . . . . . . . . . . . . . . 16
HC’s four USB states . . . . . . . . . . . . . . . . . . . 16
Generating USB traffic . . . . . . . . . . . . . . . . . . 17
PTD data structure . . . . . . . . . . . . . . . . . . . . . 19
HC’s internal FIFO buffer RAM structure . . . . 22
HC operational model. . . . . . . . . . . . . . . . . . . 28
Microprocessor loading. . . . . . . . . . . . . . . . . . 31
Internal pull-down resistors for downstream
9.1
9.2
9.3
9.4
9.5
9.6
9.7
ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Overcurrent detection and power switching
control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Suspend and wake-up . . . . . . . . . . . . . . . . . . 34
9.8
9.9
10
HC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
HC control and status registers . . . . . . . . . . . 37
HC frame counter registers. . . . . . . . . . . . . . . 44
HC Root Hub registers . . . . . . . . . . . . . . . . . . 48
HC DMA and interrupt control registers . . . . . 57
HC miscellaneous registers . . . . . . . . . . . . . . 62
HC buffer RAM control registers. . . . . . . . . . . 64
10.1
10.2
10.3
10.4
10.5
10.6
11
12
13
14
15
16
17
17.1
Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . 69
Power-on reset (POR) . . . . . . . . . . . . . . . . . . . 70
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 71
Recommended operating conditions. . . . . . . 71
Static characteristics. . . . . . . . . . . . . . . . . . . . 72
Dynamic characteristics . . . . . . . . . . . . . . . . . 74
Programmed I/O timing. . . . . . . . . . . . . . . . . . 75
© Koninklijke Philips Electronics N.V. 2003.
Printed in The Netherlands
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner.
The information presented in this document does not form part of any quotation or
contract, is believed to be accurate and reliable and may be changed without notice. No
liability will be accepted by the publisher for any consequence of its use. Publication
thereof does not convey nor imply any license under patent- or other industrial or
intellectual property rights.
Date of release: 04 July 2003
Document order number: 9397 750 11371
NXP [ NXP ]
