Philips Semiconductors
Product data
Single wire CAN transceiver
AU5790
Table 3 shows the maximum power dissipation of an AU5790 without tripping the thermal overload protection, for specified combinations of
package, board configuration, and ambient temperature.
Table 3. Maximum power dissipation
Θ
P
tot
JA
Power Dissipation Max.
T = 85 °C T = 125 °C
Thermal Resistance
a
a
Additional Foil Area for
Heat Dissipation
Board Type
SO-8 on High
K/W
103
82
mW
631
793
mW
243
305
Normal traces
Conductance Board
225 Sq. mm of copper
foil attached to pin 8.
SO-8 on Low
Conductance Board
Normal traces
163
119
399
546
153
210
225 Sq. mm of copper
attached to pin 8.
SO-8 on Very Low
Conductance Board
Normal traces
194
135
335
481
129
185
225 Sq. mm of copper
attached to pin 8.
SO-14 on High
Conductance Board
Normal traces
63
50
1032
1300
397
500
105 Sq. mm of copper
attached to each of pins
1, 7, 8, & 14.
SO-14 on Low
Conductance Board
Normal traces
103
70
631
929
243
357
105 Sq. mm of copper
attached to each of pins
1, 7, 8, & 14.
SO-14 on Very Low
Conductance Board
Normal traces
126
82
516
793
198
305
105 Sq. mm of copper
attached to each of pins
1, 7, 8, & 14.
NOTES:
1. The High Conductance board is based on modeling done to EIA/JEDEC Standard JESD51-7. The board emulated contains two one ounce
thick copper ground planes, and top surface copper conductor traces of two ounce (0.071 mm thickness of copper).
2. The Low Conductance board is based on modeling done to EIA/JEDEC Standard EIA/JESD51-3. The board does not contain any ground
planes, and the top surface copper conductor traces of two ounce (0.071 mm thickness of copper).
3. The Very Low Conductance board is based on the EIA/JESD51-3, however the thickness of the surface conductors has been reduced to
0.035 mm (also referred to as 1.0 Ounce copper).
4. The above mentioned JEDEC specifications are available from: http://www.jedec.org/
15
2001 May 18
NXP [ NXP ]
