74HC32-Q100; 74HCT32-Q100
NXP Semiconductors
Quad 2-input OR gate
5. Pinning information
5.1 Pinning
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(1) The die substrate is attached to this pad using
conductive die attach material. It cannot be used as a
supply pin or input.
Fig 4. Pin configuration SO14 and TSSOP14
Fig 5. Pin configuration DHVQFN14
5.2 Pin description
Table 2.
Symbol
1A to 4A
1B to 4B
1Y to 4Y
GND
Pin description
Pin
Description
data input
1, 4, 9, 12
2, 5, 10,13
3, 6, 8, 11
7
data input
data output
ground (0 V)
supply voltage
VCC
14
6. Functional description
Table 3.
Function table[1]
Input
nA
L
Output
nB
L
nY
L
L
H
L
H
H
H
H
H
H
[1] H = HIGH voltage level;
L = LOW voltage level;
X = don’t care.
74HC_HCT32_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 1 August 2012
3 of 15
NXP [ NXP ]
