74HC32-Q100; 74HCT32-Q100
NXP Semiconductors
Quad 2-input OR gate
Table 7.
Dynamic characteristics
GND = 0 V; CL = 50 pF; for load circuit see Figure 7.
Symbol Parameter
Conditions
25 C
40 C to +125 C Unit
Max Max
(85 C) (125 C)
Min
Typ
Max
74HCT32-Q100
[1]
tpd
propagation delay nA, nB to nY; see Figure 6
VCC = 4.5 V
-
-
-
-
11
9
24
-
30
-
36
-
ns
ns
ns
pF
VCC = 5.0 V; CL = 15 pF
[2]
[3]
tt
transition time
power dissipation per package;
capacitance VI = GND to VCC 1.5 V
VCC = 4.5 V; see Figure 6
7
15
-
19
-
22
-
CPD
28
[1] tpd is the same as tPHL and tPLH
.
[2] tt is the same as tTHL and tTLH
.
[3] CPD is used to determine the dynamic power dissipation (PD in W):
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL VCC2 fo) = sum of outputs.
11. Waveforms
ꢃ
ꢎ
ꢇꢓꢔꢉꢇꢕꢉꢖꢇꢍꢋꢌ
ꢇꢈꢉꢊꢋꢌꢍꢋꢌ
ꢃ
ꢑ
ꢀꢁꢂ
ꢌ
ꢌ
ꢏꢆꢅ
ꢏꢅꢆ
ꢃ
ꢃ
ꢄꢅ
ꢈ
ꢃ
ꢑ
ꢃ
ꢒ
ꢃ
ꢄꢆ
ꢌ
ꢌ
ꢐꢆꢅ
ꢐꢅꢆ
ꢀꢀꢀꢁꢂꢂꢃꢂꢅꢆ
Measurement points are given in Table 9.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 6. Input to output propagation delays
Table 8.
Type
Measurement points
Input
VM
Output
VM
VX
VY
74HC32-Q100
74HCT32-Q100
0.5VCC
1.3 V
0.5VCC
1.3 V
0.1VCC
0.1VCC
0.9VCC
0.9VCC
74HC_HCT32_Q100
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 1 August 2012
7 of 15
NXP [ NXP ]
