74HC273; 74HCT273
Philips Semiconductors
Octal D-type flip-flop with reset; positive-edge trigger
Table 10: Dynamic characteristics 74HCT273 …continued
Voltages are referenced to GND (ground = 0 V); tr = tf = 6 ns; CL = 50 pF unless otherwise specified; for test circuit see
Figure 10.
Symbol Parameter
trec recovery time MR to CP
tsu
Conditions
Min
+10
12
Typ
−2
5
Max
Unit
ns
VCC = 4.5 V; see Figure 8
VCC = 4.5 V; see Figure 9
VCC = 4.5 V; see Figure 9
see Figure 7
-
-
-
set-up time Dn to CP
ns
th
hold time Dn to CP
+3
−4
ns
fmax
maximum input clock frequency
VCC = 4.5 V
30
-
56
36
23
-
-
-
MHz
MHz
pF
VCC = 5.0 V; CL = 15 pF
per flip-flop; VI = GND to (VCC − 1.5 V)
[1]
CPD
power dissipation capacitance
-
Tamb = −40 °C to +85 °C
tPHL propagation delay CP to Qn
tPLH
,
VCC = 4.5 V; see Figure 7
-
-
-
-
-
-
38
43
19
ns
ns
ns
tPHL
HIGH-to-LOW propagation delay VCC = 4.5 V; see Figure 8
MR to Qn
tTHL
,
output transition time
VCC = 4.5 V; see Figure 7
tTLH
tW
pulse width
clock HIGH or LOW
master reset LOW
VCC = 4.5 V; see Figure 7
VCC = 4.5 V; see Figure 8
VCC = 4.5 V; see Figure 8
VCC = 4.5 V; see Figure 9
VCC = 4.5 V; see Figure 9
VCC = 4.5 V; see Figure 7
20
20
13
15
3
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
trec
tsu
recovery time MR to CP
set-up time Dn to CP
hold time Dn to CP
maximum input clock frequency
ns
ns
th
ns
fmax
24
MHz
Tamb = −40 °C to +125 °C
tPHL propagation delay CP to Qn
tPLH
,
VCC = 4.5 V; see Figure 7
-
-
-
-
-
-
45
51
22
ns
ns
ns
tPHL
HIGH-to-LOW propagation delay VCC = 4.5 V; see Figure 8
MR to Qn
tTHL
,
output transition time
VCC = 4.5 V; see Figure 7
tTLH
tW
pulse width
clock HIGH or LOW
master reset LOW
VCC = 4.5 V; see Figure 7
VCC = 4.5 V; see Figure 8
VCC = 4.5 V; see Figure 8
VCC = 4.5 V; see Figure 9
VCC = 4.5 V; see Figure 9
VCC = 4.5 V; see Figure 7
24
24
15
18
3
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
trec
tsu
recovery time MR to CP
set-up time Dn to CP
hold time Dn to CP
maximum input clock frequency
ns
ns
th
ns
fmax
20
MHz
[1] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
74HC_HCT273_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 24 January 2006
15 of 26
NXP [ NXP ]
