74HC273; 74HCT273
Philips Semiconductors
Octal D-type flip-flop with reset; positive-edge trigger
Table 9:
Dynamic characteristics 74HC273 …continued
Voltages are referenced to GND (ground = 0 V); tr = tf = 6 ns; CL = 50 pF unless otherwise specified; for test circuit see
Figure 10.
Symbol Parameter
trec recovery time MR to CP
Conditions
see Figure 8
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 9
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 9
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 7
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
Min
Typ
Max
Unit
65
13
11
-
-
-
-
-
-
ns
ns
ns
tsu
set-up time Dn to CP
75
15
13
-
-
-
-
-
-
ns
ns
ns
th
hold time Dn to CP
3
3
3
-
-
-
-
-
-
ns
ns
ns
fmax
maximum input clock frequency
4.8
24
28
-
-
-
-
-
-
MHz
MHz
MHz
Tamb = −40 °C to +125 °C
tPHL propagation delay CP to Qn
tPLH
,
see Figure 7
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
-
-
-
-
-
-
225
45
ns
ns
ns
38
tPHL
HIGH-to-LOW propagation delay see Figure 8
MR to Qn
VCC = 2.0 V
-
-
-
-
-
-
225
45
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
38
tTHL
tTLH
,
output transition time
see Figure 7
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
-
-
-
-
-
-
110
22
ns
ns
ns
19
tW
pulse width
clock HIGH or LOW
see Figure 7
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 8
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
120
24
-
-
-
-
-
-
ns
ns
ns
20
master reset LOW
90
18
15
-
-
-
-
-
-
ns
ns
ns
74HC_HCT273_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 24 January 2006
13 of 26
NXP [ NXP ]
