74HC273; 74HCT273
Philips Semiconductors
Octal D-type flip-flop with reset; positive-edge trigger
Table 9:
Dynamic characteristics 74HC273 …continued
Voltages are referenced to GND (ground = 0 V); tr = tf = 6 ns; CL = 50 pF unless otherwise specified; for test circuit see
Figure 10.
Symbol Parameter
trec recovery time MR to CP
Conditions
Min
Typ
Max
Unit
see Figure 8
VCC = 2.0 V
+50
+10
+9
−6
−2
−2
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
tsu
set-up time Dn to CP
see Figure 9
VCC = 2.0 V
60
12
10
11
4
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
3
th
hold time Dn to CP
see Figure 9
VCC = 2.0 V
+3
+3
+3
−6
−2
−2
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
fmax
maximum input clock frequency
see Figure 7
VCC = 2.0 V
6.0
30
-
20.6
103
66
-
-
-
-
-
MHz
MHz
MHz
MHz
pF
VCC = 4.5 V
VCC = 5 V; CL = 15 pF
VCC = 6.0 V
35
-
122
20
[1]
CPD
power dissipation capacitance
per flip-flop; VI = GND to VCC
Tamb = −40 °C to +85 °C
tPHL propagation delay CP to Qn
tPLH
,
see Figure 7
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
-
-
-
-
-
-
185
37
ns
ns
ns
31
tPHL
HIGH-to-LOW propagation delay see Figure 8
MR to Qn
VCC = 2.0 V
-
-
-
-
-
-
185
37
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
31
tTHL
tTLH
,
output transition time
see Figure 7
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
-
-
-
-
-
-
95
19
15
ns
ns
ns
tW
pulse width
clock HIGH or LOW
see Figure 7
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 8
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
100
20
-
-
-
-
-
-
ns
ns
ns
17
master reset LOW
75
15
13
-
-
-
-
-
-
ns
ns
ns
74HC_HCT273_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 24 January 2006
12 of 26
NXP [ NXP ]
