74HC273; 74HCT273
Philips Semiconductors
Octal D-type flip-flop with reset; positive-edge trigger
Table 9:
Dynamic characteristics 74HC273 …continued
Voltages are referenced to GND (ground = 0 V); tr = tf = 6 ns; CL = 50 pF unless otherwise specified; for test circuit see
Figure 10.
Symbol Parameter
trec recovery time MR to CP
Conditions
see Figure 8
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 9
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 9
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 7
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
Min
Typ
Max
Unit
75
15
13
-
-
-
-
-
-
ns
ns
ns
tsu
set-up time Dn to CP
90
18
15
-
-
-
-
-
-
ns
ns
ns
th
hold time Dn to CP
3
3
3
-
-
-
-
-
-
ns
ns
ns
fmax
maximum input clock frequency
4.0
20
24
-
-
-
-
-
-
MHz
MHz
MHz
[1] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
∑(CL × VCC2 × fo) = sum of outputs.
Table 10: Dynamic characteristics 74HCT273
Voltages are referenced to GND (ground = 0 V); tr = tf = 6 ns; CL = 50 pF unless otherwise specified; for test circuit see
Figure 10.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = 25 °C
tPHL
tPLH
,
propagation delay CP to Qn
see Figure 7
VCC = 4.5 V
-
-
16
15
30
-
ns
ns
VCC = 5 V; CL = 15 pF
tPHL
HIGH-to-LOW propagation delay see Figure 8
MR to Qn
VCC = 4.5 V
-
-
-
23
20
7
34
-
ns
ns
ns
VCC = 5 V; CL = 15 pF
tTHL
,
output transition time
VCC = 4.5 V; see Figure 7
15
tTLH
tW
pulse width
clock HIGH or LOW
master reset LOW
VCC = 4.5 V; see Figure 7
VCC = 4.5 V; see Figure 8
16
16
9
8
-
-
ns
ns
74HC_HCT273_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 24 January 2006
14 of 26
NXP [ NXP ]
