NXP Semiconductors
74HC32; 74HCT32
Quad 2-input OR gate
5. Pinning information
5.1 Pinning
terminal 1
index area
1B
1Y
2A
2B
2B
2Y
GND
5
6
7
001aad101
1A
1B
1Y
2A
1
2
3
4
14 V
CC
13 4B
12 4A
2
3
4
5
6
7
GND
3Y
8
14 V
CC
13 4B
12 4A
11 4Y
10 3B
9
3A
32
11 4Y
10 3B
9
8
3A
3Y
GND
(1)
2Y
1
1A
32
001aad102
Transparent top view
(1) The die substrate is attached to this pad using
conductive die attach material. It cannot be used as a
supply pin or input.
Fig 4.
Pin configuration DIP14, SO14 and (T)SSOP14
Fig 5.
Pin configuration DHVQFN14
5.2 Pin description
Table 2.
Symbol
1A to 4A
1B to 4B
1Y to 4Y
GND
V
CC
Pin description
Pin
1, 4, 9, 12
2, 5, 10,13
3, 6, 8, 11
7
14
Description
data input
data input
data output
ground (0 V)
supply voltage
6. Functional description
Table 3.
Input
nA
L
L
H
H
[1]
H = HIGH voltage level;
L = LOW voltage level;
X = don’t care.
Function table
Output
nB
L
H
L
H
nY
L
H
H
H
74HC_HCT32
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 4 September 2012
3 of 17
PHILIPS [ NXP SEMICONDUCTORS ]
