Philips Semiconductors
Product specification
4-bit parallel access shift register
74HC/HCT195
AC WAVEFORMS
(1) HC : VM = 50%; VI = GND to VCC
.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3V; VI = GND to 3 V.
HCT: VM = 1.3V; VI = GND to 3 V.
Fig.7 Waveforms showing the master reset
(MR) pulse width, the master reset to output
(Qn) propagation delays and the master
reset to clock (CP) removal time
Fig.6 Waveforms showing the clock (CP) to
output (Qn) propagation delays, the clock
pulse width, the output transition times and
the maximum clock frequency.
The shaded areas indicate when the input is permitted to
change for predictable output performance.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3V; VI = GND to 3 V.
Fig.8 Waveforms showing the data set-up
and hold times for J, K and Dn inputs.
The shaded areas indicate when the input is permitted to
change for predictable output performance.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3V; VI = GND to 3 V.
Fig.9 Waveforms showing the set-up and hold
times from the parallel enable input
(PE) to the clock (CP).
December 1990
8
NXP [ NXP ]
