74HC166-Q100; 74HCT166-Q100
NXP Semiconductors
8-bit parallel-in/serial out shift register
V
I
MR input
V
M
GND
t
W
t
rec
V
I
V
CP input
M
GND
t
PHL
V
OH
Q7 output
V
M
V
OL
aaa-008822
Measurement points are given in Table 8.
OL and VOH are typical voltage output levels that occur with the output load.
V
Fig 8. Master reset (MR) pulse width, MR to output (Q7) propagation delay and MR to clock (CP) recovery time.
see note (1)
V
I
CE input
GND
V
M
t
su
t
t
t
su
su
t
t
t
t
t
h
h
h
V
I
PE input
GND
V
M
t
su
su
h
h
V
I
stable
Dn input
GND
V
M
t
su
t
h
V
I
stable
DS input
GND
V
M
t
su
t
t
W
h
V
I
CP input
GND
V
M
aaa-008823
condition: MR = HIGH
The shaded areas indicate when the input is permitted to change for predictable output performance
Measurement points are given in Table 8.
(1) CE may change only from HIGH-to-LOW while CP is LOW
Fig 9. Set-up and hold times
74HC_HCT166_Q100
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 25 September 2013
12 of 19
NXP [ NXP ]
