74HC166-Q100; 74HCT166-Q100
NXP Semiconductors
8-bit parallel-in/serial out shift register
Table 7.
Dynamic characteristics …continued
GND (ground = 0 V); tr = tf = 6 ns: CL = 50 pF unless otherwise specified; for test circuit, see Figure 10
Symbol Parameter
Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Max Min Max
Min Typ Max
th
hold time
Dn, CE to CP; see Figure 9
VCC = 2.0 V
2
2
2
8
3
2
-
-
-
2
2
2
-
-
-
2
2
2
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
PE to CP; see Figure 9
VCC = 2.0 V
0
0
0
28
10
8
-
-
-
0
0
0
-
-
-
0
0
0
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
fmax
maximum
frequency
CP input; see Figure 7
VCC = 2.0 V
6
19
57
63
68
41
-
-
-
-
-
4.8
24
-
-
-
-
-
-
4
-
-
-
-
-
MHz
MHz
MHz
MHz
pF
VCC = 4.5 V
30
-
20
-
VCC = 5.0 V; CL = 15 pF
VCC = 6.0 V
35
-
28
-
24
-
[3]
[1]
CPD
power
dissipation
capacitance
per package;
VI = GND to VCC
74HCT166-Q100
tpd
propagation
delay
CP to Q7; see Figure 7
VCC = 4.5 V
-
23
20
40
-
-
-
50
50
19
-
-
-
60
60
22
ns
ns
VCC = 5.0 V; CL = 15 pF
MR to Q7; see Figure 8
VCC = 4.5 V
-
-
-
-
-
-
-
-
-
-
-
-
22
19
40
ns
ns
VCC = 5.0 V; CL = 15 pF
output; see Figure 7
VCC = 4.5 V
-
-
[2]
tt
transition
time
7
15
ns
tW
pulse width
CP input HIGH or LOW;
see Figure 7
VCC = 4.5 V
20
25
0
9
-
-
-
-
-
-
-
25
31
0
-
-
-
-
-
-
-
30
38
0
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
MR input LOW; see Figure 8
VCC = 4.5 V
11
7
8
trec
recovery time MR to CP; see Figure 8
VCC = 4.5 V
tsu
set-up time
Dn, CE to CP; see Figure 9
VCC = 4.5 V
16
30
0
20
38
0
24
45
0
PE to CP; see Figure 9
VCC = 4.5 V
15
3
13
th
hold time
Dn, CE to CP; see Figure 9
VCC = 4.5 V
PE to CP; see Figure 9
VCC = 4.5 V
0
0
0
74HC_HCT166_Q100
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Product data sheet
Rev. 1 — 25 September 2013
10 of 19
NXP [ NXP ]
