74HC166-Q100; 74HCT166-Q100
NXP Semiconductors
8-bit parallel-in/serial out shift register
Table 7.
Dynamic characteristics …continued
GND (ground = 0 V); tr = tf = 6 ns: CL = 50 pF unless otherwise specified; for test circuit, see Figure 10
Symbol Parameter
Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Max Min Max
Min Typ Max
fmax
maximum
frequency
CP input; see Figure 7
VCC = 4.5 V
25
-
45
50
41
-
-
-
20
-
-
-
17
-
-
-
MHz
MHz
pF
VCC = 5.0 V; CL = 15 pF
-
-
-
-
[3]
CPD
power
per package;
-
dissipation
capacitance
VI = GND to VCC
[1] tpd is the same as tPHL and tPLH
.
[2] tt is the same as tTHL and tTLH
.
[3] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
(CL VCC2 fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in V.
11. Waveforms
1/f
max
V
I
CP input
V
M
GND
t
W
t
t
PLH
PHL
V
OH
90 %
90 %
Q7 output
V
M
10 %
10 %
TLH
V
OL
t
t
THL
aaa-008821
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 7. Clock (CP) to output (Q7) propagation delays, pulse width, output transition times and maximum
frequency
74HC_HCT166_Q100
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 25 September 2013
11 of 19
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