NXP Semiconductors
74HC165-Q100; 74HCT165-Q100
8-bit parallel-in/serial out shift register
V
I
CP, CE input
GND
(1)
V
M
t
h
t
su
V
I
DS input
GND
t
su
V
I
CP, CE input
GND
V
M
t
W
V
M
t
su
t
h
mna990
The shaded areas indicate when the input is permitted to change for predictable output performance
Measurement points are given in
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
(1) CE may change only from HIGH-to-LOW while CP is LOW, see
Fig 10. Waveforms showing set-up and hold times
V
I
Dn input
GND
t
su
V
I
PL input
GND
V
M
V
M
mna991
V
M
V
M
t
h
t
su
t
h
Measurement points are given in
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
Fig 11. The set-up and hold times from the data inputs (Dn) to the parallel load input (PL)
Table 8.
Type
74HC165-Q100
74HCT165-Q100
Measurement points
Input
V
I
V
CC
3V
V
M
0.5V
CC
1.3 V
Output
V
M
0.5V
CC
1.3 V
74HC_HCT165_Q100
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 17 July 2012
13 of 21
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